//////////////////////////////////////////////////////////////////
// Translated Verilog Source File
// Auto-Generated By Xilinx's Blf2lang.
// Copyright (c) 2003. Xilinx, Inc.
//////////////////////////////////////////////////////////////////
//Main registers



`timescale 1ns/1ns

module m220 ( adder_left2_,adder_left1_,adder_right2_,adder_right1_,and_enable,tt_ls_in,carry_in_,mq,sr,sc,data,input_bus,mem,data_addr,a_src0,a_src1,a_src2,b_src0,b_src1,b_src2,shift0,shift1,shift2,mb_load,ma_load,ac_load,pc_load,mb,ma,ac,pc,adder_,carry_out_ );
    input adder_left2_;
    input adder_left1_;
    input adder_right2_;
    input adder_right1_;
    input and_enable;
    input tt_ls_in;
    input carry_in_;
    input mq;
    input sr;
    input sc;
    input data;
    input input_bus;
    input mem;
    input data_addr;
    input a_src0;
    input a_src1;
    input a_src2;
    input b_src0;
    input b_src1;
    input b_src2;
    input shift0;
    input shift1;
    input shift2;
    input mb_load;
    input ma_load;
    input ac_load;
    input pc_load;
    output mb;
    output ma;
    output ac;
    output pc;
    output adder_;
    output carry_out_;

// Global and port properties...

// Declarations for internal nets...
    wire a_;
    wire b_;
    wire regbus;
    wire adder__xcX1;
    wire adder__xcX2;
    wire carry_out__xcX1;
    wire carry_out__xcX2;
    wire adder__xcBUF;
    wire carry_out__xcBUF;
    wire mb_xcD;
    wire mb_xcQ;
    wire mb_xcCLOCK;
    wire ma_xcD;
    wire ma_xcQ;
    wire ma_xcCLOCK;
    wire ac_xcD;
    wire ac_xcQ;
    wire ac_xcCLOCK;
    wire pc_xcD;
    wire pc_xcQ;
    wire pc_xcCLOCK;

// Properties on instances and internal nets...

//Logic implementation...
assign mb_xcCLOCK =  ((mb_load));
assign mb_xcD = ((regbus));
G_DEC mb_B2LINST_1 ( .q(mb_xcQ), .d(mb_xcD), .clk(mb_xcCLOCK), .e(1'b1), .c(1'b0));
assign mb =  (mb_xcQ);

assign ma_xcCLOCK =  ((ma_load));
assign ma_xcD = ((regbus));
G_DEC ma_B2LINST_2 ( .q(ma_xcQ), .d(ma_xcD), .clk(ma_xcCLOCK), .e(1'b1), .c(1'b0));
assign ma =  (ma_xcQ);

assign ac_xcCLOCK =  ((ac_load));
assign ac_xcD = ((regbus));
G_DEC ac_B2LINST_3 ( .q(ac_xcQ), .d(ac_xcD), .clk(ac_xcCLOCK), .e(1'b1), .c(1'b0));
assign ac =  (ac_xcQ);

assign pc_xcCLOCK =  ((pc_load));
assign pc_xcD = ((regbus));
G_DEC pc_B2LINST_4 ( .q(pc_xcQ), .d(pc_xcD), .clk(pc_xcCLOCK), .e(1'b1), .c(1'b0));
assign pc =  (pc_xcQ);

assign adder__xcBUF = (adder__xcX1  ^  adder__xcX2);
assign adder__xcX1 = (( ~(a_) & b_)
       |  (a_ &  ~(b_)));
assign adder__xcX2 = (~ (carry_in_));
assign adder_ = (adder__xcBUF);

assign carry_out__xcBUF = (carry_out__xcX1  ^  carry_out__xcX2);
assign carry_out__xcX1 = (( ~(a_) &  ~(carry_in_))
       |  ( ~(b_) &  ~(carry_in_))
       |  (a_ & b_ & carry_in_));
assign carry_out__xcX2 = (( ~(a_) & b_ &  ~(carry_in_))
       |  (a_ &  ~(b_) &  ~(carry_in_)));
assign carry_out_ = (carry_out__xcBUF);

assign a_ = (( ~(a_src0) &  ~(a_src2) & ac_xcQ)
       |  ( ~(a_src0) &  ~(a_src1) &  ~(ac_xcQ))
       |  ( ~(a_src1) &  ~(a_src2) &  ~(sr))
       |  (a_src0 & a_src1 &  ~(a_src2) &  ~(data))
       |  (a_src0 & a_src1 & a_src2 &  ~(input_bus))
       |  ( ~(a_src0) & a_src1 & a_src2 &  ~(mq))
       |  (a_src0 &  ~(a_src1) & a_src2 &  ~(sc)));

assign b_ = ~ ((b_src0 &  ~(b_src1) &  ~(b_src2) & data_addr)
       |  ( ~(b_src0) &  ~(b_src1) & b_src2 & ma_xcQ)
       |  ( ~(b_src0) & b_src1 & b_src2 & mem)
       |  ( ~(b_src0) & b_src1 &  ~(b_src2) & pc_xcQ));

assign regbus = ~ ((and_enable &  ~(mb_xcQ))
       |  (adder_left1_ &  ~(shift0) & shift1 & shift2)
       |  (adder_right1_ &  ~(shift0) &  ~(shift1) & shift2)
       |  (adder_right2_ &  ~(shift0) & shift1 &  ~(shift2))
       |  (adder_left2_ & shift0 &  ~(shift1) &  ~(shift2))
       |  (adder__xcBUF &  ~(shift0) &  ~(shift1) &  ~(shift2))
       |  (shift0 &  ~(shift1) & shift2 & tt_ls_in));

endmodule