//////////////////////////////////////////////////////////////////
// Translated Verilog Source File
// Auto-Generated By Xilinx's Blf2lang.
// Copyright (c) 2003. Xilinx, Inc.
//////////////////////////////////////////////////////////////////
//State Machine



`timescale 1ns/1ns

module pdp8 ( clock,brkrq,intrq,halt,mb0,mb1,mb2,mb3,mem,a_src0,a_src1,a_src2,b_src0,b_src1,b_src2,shift0,shift1,shift2,mb_load,ma_load,ac_load,pc_load,ts1,ts2,ts3,ts4,fetch,defer,exec,break,intr,ir0,ir1,ir2 );
    input clock;
    input brkrq;
    input intrq;
    input halt;
    input mb0;
    input mb1;
    input mb2;
    input mb3;
    input mem;
    input a_src0;
    input a_src1;
    input a_src2;
    input b_src0;
    input b_src1;
    input b_src2;
    input shift0;
    input shift1;
    input shift2;
    input mb_load;
    input ma_load;
    input ac_load;
    input pc_load;
    output ts1;
    output ts2;
    output ts3;
    output ts4;
    output fetch;
    output defer;
    output exec;
    output break;
    output intr;
    output ir0;
    output ir1;
    output ir2;

// Global and port properties...

// Declarations for internal nets...
    wire ts1_xcD;
    wire ts1_xcQ;
    wire ts1_xcCLOCK;
    wire ts2_xcD;
    wire ts2_xcQ;
    wire ts2_xcCLOCK;
    wire ts3_xcD;
    wire ts3_xcQ;
    wire ts3_xcCLOCK;
    wire ts4_xcD;
    wire ts4_xcQ;
    wire ts4_xcCLOCK;
    wire fetch_xcD;
    wire fetch_xcQ;
    wire fetch_xcCLOCK;
    wire defer_xcD;
    wire defer_xcQ;
    wire defer_xcCLOCK;
    wire exec_xcD;
    wire exec_xcQ;
    wire exec_xcCLOCK;
    wire break_xcD;
    wire break_xcQ;
    wire break_xcCLOCK;
    wire intr_xcD;
    wire intr_xcQ;
    wire intr_xcCLOCK;
    wire ir0_xcD;
    wire ir0_xcQ;
    wire ir0_xcCLOCK;
    wire ir1_xcD;
    wire ir1_xcQ;
    wire ir1_xcCLOCK;
    wire ir2_xcD;
    wire ir2_xcQ;
    wire ir2_xcCLOCK;

// Properties on instances and internal nets...

//Logic implementation...
assign ts1_xcCLOCK =  ((clock));
assign ts1_xcD = ((brkrq &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  (defer_xcQ &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  ( ~(halt) &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  (intrq &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  (fetch_xcQ &  ~(ir0_xcQ) &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  (fetch_xcQ &  ~(ir1_xcQ) &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ));
G_DEC ts1_B2LINST_1 ( .q(ts1_xcQ), .d(ts1_xcD), .clk(ts1_xcCLOCK), .e(1'b1), .c(1'b0));
assign ts1 =  (ts1_xcQ);

assign ts2_xcCLOCK =  ((clock));
assign ts2_xcD = ((ts1_xcQ &  ~(ts2_xcQ) &  ~(ts3_xcQ) &  ~(ts4_xcQ)));
G_DEC ts2_B2LINST_2 ( .q(ts2_xcQ), .d(ts2_xcD), .clk(ts2_xcCLOCK), .e(1'b1), .c(1'b0));
assign ts2 =  (ts2_xcQ);

assign ts3_xcCLOCK =  ((clock));
assign ts3_xcD = (( ~(ts1_xcQ) & ts2_xcQ &  ~(ts3_xcQ) &  ~(ts4_xcQ)));
G_DEC ts3_B2LINST_3 ( .q(ts3_xcQ), .d(ts3_xcD), .clk(ts3_xcCLOCK), .e(1'b1), .c(1'b0));
assign ts3 =  (ts3_xcQ);

assign ts4_xcCLOCK =  ((clock));
assign ts4_xcD = (( ~(ts1_xcQ) &  ~(ts2_xcQ) & ts3_xcQ &  ~(ts4_xcQ))
       |  (halt &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ));
G_DEC ts4_B2LINST_4 ( .q(ts4_xcQ), .d(ts4_xcD), .clk(ts4_xcCLOCK), .e(1'b1), .c(1'b0));
assign ts4 =  (ts4_xcQ);

assign fetch_xcCLOCK =  ((clock));
assign fetch_xcD = (( ~(halt) &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ));
G_DEC fetch_B2LINST_5 ( .q(fetch_xcQ), .d(fetch_xcD), .clk(fetch_xcCLOCK), .e(1'b1), .c(1'b0));
assign fetch =  (fetch_xcQ);

assign defer_xcCLOCK =  ((clock));
assign defer_xcD = ((fetch_xcQ &  ~(ir0_xcQ) & mb3 &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  (fetch_xcQ &  ~(ir1_xcQ) & mb3 &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ));
G_DEC defer_B2LINST_6 ( .q(defer_xcQ), .d(defer_xcD), .clk(defer_xcCLOCK), .e(1'b1), .c(1'b0));
assign defer =  (defer_xcQ);

assign exec_xcCLOCK =  ((clock));
assign exec_xcD = ((defer_xcQ &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  (fetch_xcQ &  ~(ir0_xcQ) &  ~(mb3) &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ)
       |  (fetch_xcQ &  ~(ir1_xcQ) &  ~(mb3) &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ));
G_DEC exec_B2LINST_7 ( .q(exec_xcQ), .d(exec_xcD), .clk(exec_xcCLOCK), .e(1'b1), .c(1'b0));
assign exec =  (exec_xcQ);

assign break_xcCLOCK =  ((clock));
assign break_xcD = ((brkrq &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ));
G_DEC break_B2LINST_8 ( .q(break_xcQ), .d(break_xcD), .clk(break_xcCLOCK), .e(1'b1), .c(1'b0));
assign break =  (break_xcQ);

assign intr_xcCLOCK =  ((clock));
assign intr_xcD = ((intrq &  ~(ts1_xcQ) &  ~(ts2_xcQ) &  ~(ts3_xcQ) & ts4_xcQ));
G_DEC intr_B2LINST_9 ( .q(intr_xcQ), .d(intr_xcD), .clk(intr_xcCLOCK), .e(1'b1), .c(1'b0));
assign intr =  (intr_xcQ);

assign ir0_xcCLOCK =  ((clock));
assign ir0_xcD = ((fetch_xcQ & mb0 &  ~(ts1_xcQ) & ts2_xcQ &  ~(ts3_xcQ) &  ~(ts4_xcQ)));
G_DEC ir0_B2LINST_10 ( .q(ir0_xcQ), .d(ir0_xcD), .clk(ir0_xcCLOCK), .e(1'b1), .c(1'b0));
assign ir0 =  (ir0_xcQ);

assign ir1_xcCLOCK =  ((clock));
assign ir1_xcD = ((fetch_xcQ & mb1 &  ~(ts1_xcQ) & ts2_xcQ &  ~(ts3_xcQ) &  ~(ts4_xcQ)));
G_DEC ir1_B2LINST_11 ( .q(ir1_xcQ), .d(ir1_xcD), .clk(ir1_xcCLOCK), .e(1'b1), .c(1'b0));
assign ir1 =  (ir1_xcQ);

assign ir2_xcCLOCK =  ((clock));
assign ir2_xcD = ((fetch_xcQ & mb2 &  ~(ts1_xcQ) & ts2_xcQ &  ~(ts3_xcQ) &  ~(ts4_xcQ)));
G_DEC ir2_B2LINST_12 ( .q(ir2_xcQ), .d(ir2_xcD), .clk(ir2_xcCLOCK), .e(1'b1), .c(1'b0));
assign ir2 =  (ir2_xcQ);

endmodule