//////////////////////////////////////////////////////////////////
// Translated Verilog Source File
// Auto-Generated By Xilinx's Blf2lang.
// Copyright (c) 2003. Xilinx, Inc.
//////////////////////////////////////////////////////////////////
//Main register bus



`timescale 1ns/1ns

module regbus ( clock1,r0,r1,r2,r3,x0,x1,x2,ea0,ea1,ea2,sr,sl,inp0,inp1,inp2,sw0,sw1,sw2,mem0,mem1,mem2,mb0,mb1,mb2,ma0,ma1,ma2,ac0,ac1,ac2,pc0,pc1,pc2 );
    input clock1;
    input r0;
    input r1;
    input r2;
    input r3;
    input x0;
    input x1;
    input x2;
    input ea0;
    input ea1;
    input ea2;
    input sr;
    input sl;
    input inp0;
    input inp1;
    input inp2;
    input sw0;
    input sw1;
    input sw2;
    inout mem0;
    inout mem1;
    inout mem2;
    inout mb0;
    inout mb1;
    inout mb2;
    inout ma0;
    inout ma1;
    inout ma2;
    inout ac0;
    inout ac1;
    inout ac2;
    inout pc0;
    inout pc1;
    inout pc2;

// Global and port properties...

// Declarations for internal nets...
    wire f0;
    wire f1;
    wire f2;
    wire mux0;
    wire mux1;
    wire mux2;
    wire AIM_0_DATAA0;
    wire AIM_0_DATAA1;
    wire AIM_0_DATAA2;
    wire AIM_0_DATAB0;
    wire AIM_0_DATAB1;
    wire AIM_0_DATAB2;
    wire AIM_0_ADD_SUB;
    wire AIM_0_RESULT0;
    wire AIM_0_RESULT1;
    wire AIM_0_RESULT2;
    wire mem0_xcD;
    wire mem0_xcQ;
    wire mem0_xcCLOCK;
    wire mem0_xcR;
    wire mem1_xcD;
    wire mem1_xcQ;
    wire mem1_xcCLOCK;
    wire mem1_xcR;
    wire mem2_xcD;
    wire mem2_xcQ;
    wire mem2_xcCLOCK;
    wire mem2_xcR;
    wire mb0_xcD;
    wire mb0_xcQ;
    wire mb0_xcCLOCK;
    wire mb0_xcR;
    wire mb1_xcD;
    wire mb1_xcQ;
    wire mb1_xcCLOCK;
    wire mb1_xcR;
    wire mb2_xcD;
    wire mb2_xcQ;
    wire mb2_xcCLOCK;
    wire mb2_xcR;
    wire ma0_xcD;
    wire ma0_xcQ;
    wire ma0_xcCLOCK;
    wire ma0_xcR;
    wire ma1_xcD;
    wire ma1_xcQ;
    wire ma1_xcCLOCK;
    wire ma1_xcR;
    wire ma2_xcD;
    wire ma2_xcQ;
    wire ma2_xcCLOCK;
    wire ma2_xcR;
    wire ac0_xcD;
    wire ac0_xcQ;
    wire ac0_xcCLOCK;
    wire ac0_xcR;
    wire ac1_xcD;
    wire ac1_xcQ;
    wire ac1_xcCLOCK;
    wire ac1_xcR;
    wire ac2_xcD;
    wire ac2_xcQ;
    wire ac2_xcCLOCK;
    wire ac2_xcR;
    wire pc0_xcD;
    wire pc0_xcQ;
    wire pc0_xcCLOCK;
    wire pc0_xcR;
    wire pc1_xcD;
    wire pc1_xcQ;
    wire pc1_xcCLOCK;
    wire pc1_xcR;
    wire pc2_xcD;
    wire pc2_xcQ;
    wire pc2_xcCLOCK;
    wire pc2_xcR;

// Properties on instances and internal nets...

//Logic implementation...
aim_add_sub_3 AIM_0 (
   .DATAA0(AIM_0_DATAA0)
   , .DATAA1(AIM_0_DATAA1)
   , .DATAA2(AIM_0_DATAA2)
   , .DATAB0(AIM_0_DATAB0)
   , .DATAB1(AIM_0_DATAB1)
   , .DATAB2(AIM_0_DATAB2)
   , .ADD_SUB(AIM_0_ADD_SUB)
   , .RESULT0(AIM_0_RESULT0)
   , .RESULT1(AIM_0_RESULT1)
   , .RESULT2(AIM_0_RESULT2));

assign mem0_xcCLOCK =  ((clock1));
assign mem0_xcR =  (1'b0);
assign mem0_xcD = ((mem0 &  ~(r0))
       |  (mem0 &  ~(r1))
       |  (mb0 & r0 & r1));
G_DEC mem0_B2LINST_1 ( .q(mem0_xcQ), .d(mem0_xcD), .clk(mem0_xcCLOCK), .e(1'b1), .c(mem0_xcR));
assign mem0 =  (mem0_xcQ);

assign mem1_xcCLOCK =  ((clock1));
assign mem1_xcR =  (1'b0);
assign mem1_xcD = ((mem1 &  ~(r0))
       |  (mem1 &  ~(r1))
       |  (mb1 & r0 & r1));
G_DEC mem1_B2LINST_2 ( .q(mem1_xcQ), .d(mem1_xcD), .clk(mem1_xcCLOCK), .e(1'b1), .c(mem1_xcR));
assign mem1 =  (mem1_xcQ);

assign mem2_xcCLOCK =  ((clock1));
assign mem2_xcR =  (1'b0);
assign mem2_xcD = ((mem2 &  ~(r0))
       |  (mem2 &  ~(r1))
       |  (mb2 & r0 & r1));
G_DEC mem2_B2LINST_3 ( .q(mem2_xcQ), .d(mem2_xcD), .clk(mem2_xcCLOCK), .e(1'b1), .c(mem2_xcR));
assign mem2 =  (mem2_xcQ);

assign mb0_xcCLOCK =  ((clock1));
assign mb0_xcR =  (1'b0);
assign mb0_xcD = ((mb0 & r2)
       |  (mb0 & r0 & r1)
       |  (mb0 &  ~(r0) &  ~(r1))
       |  (mb0 & r0 & r3)
       |  (mem0 &  ~(r0) & r1 &  ~(r2))
       |  (f0 & r0 &  ~(r1) &  ~(r2) &  ~(r3)));
G_DEC mb0_B2LINST_4 ( .q(mb0_xcQ), .d(mb0_xcD), .clk(mb0_xcCLOCK), .e(1'b1), .c(mb0_xcR));
assign mb0 =  (mb0_xcQ);

assign mb1_xcCLOCK =  ((clock1));
assign mb1_xcR =  (1'b0);
assign mb1_xcD = ((mb1 & r2)
       |  (mb1 & r0 & r1)
       |  (mb1 &  ~(r0) &  ~(r1))
       |  (mb1 & r0 & r3)
       |  (mem1 &  ~(r0) & r1 &  ~(r2))
       |  (f1 & r0 &  ~(r1) &  ~(r2) &  ~(r3)));
G_DEC mb1_B2LINST_5 ( .q(mb1_xcQ), .d(mb1_xcD), .clk(mb1_xcCLOCK), .e(1'b1), .c(mb1_xcR));
assign mb1 =  (mb1_xcQ);

assign mb2_xcCLOCK =  ((clock1));
assign mb2_xcR =  (1'b0);
assign mb2_xcD = ((mb2 & r2)
       |  (mb2 & r0 & r1)
       |  (mb2 &  ~(r0) &  ~(r1))
       |  (mb2 & r0 & r3)
       |  (mem2 &  ~(r0) & r1 &  ~(r2))
       |  (f2 & r0 &  ~(r1) &  ~(r2) &  ~(r3)));
G_DEC mb2_B2LINST_6 ( .q(mb2_xcQ), .d(mb2_xcD), .clk(mb2_xcCLOCK), .e(1'b1), .c(mb2_xcR));
assign mb2 =  (mb2_xcQ);

assign ma0_xcCLOCK =  ((clock1));
assign ma0_xcR =  (1'b0);
assign ma0_xcD = ((ma0 & r2)
       |  (ma0 &  ~(r3))
       |  (f0 & r0 &  ~(r2) & r3)
       |  (mem0 &  ~(r0) & r1 &  ~(r2) & r3)
       |  (ea0 &  ~(r0) &  ~(r1) &  ~(r2) & r3));
G_DEC ma0_B2LINST_7 ( .q(ma0_xcQ), .d(ma0_xcD), .clk(ma0_xcCLOCK), .e(1'b1), .c(ma0_xcR));
assign ma0 =  (ma0_xcQ);

assign ma1_xcCLOCK =  ((clock1));
assign ma1_xcR =  (1'b0);
assign ma1_xcD = ((ma1 & r2)
       |  (ma1 &  ~(r3))
       |  (f1 & r0 &  ~(r2) & r3)
       |  (mem1 &  ~(r0) & r1 &  ~(r2) & r3)
       |  (ea1 &  ~(r0) &  ~(r1) &  ~(r2) & r3));
G_DEC ma1_B2LINST_8 ( .q(ma1_xcQ), .d(ma1_xcD), .clk(ma1_xcCLOCK), .e(1'b1), .c(ma1_xcR));
assign ma1 =  (ma1_xcQ);

assign ma2_xcCLOCK =  ((clock1));
assign ma2_xcR =  (1'b0);
assign ma2_xcD = ((ma2 & r2)
       |  (ma2 &  ~(r3))
       |  (f2 & r0 &  ~(r2) & r3)
       |  (mem2 &  ~(r0) & r1 &  ~(r2) & r3)
       |  (ea2 &  ~(r0) &  ~(r1) &  ~(r2) & r3));
G_DEC ma2_B2LINST_9 ( .q(ma2_xcQ), .d(ma2_xcD), .clk(ma2_xcCLOCK), .e(1'b1), .c(ma2_xcR));
assign ma2 =  (ma2_xcQ);

assign ac0_xcCLOCK =  ((clock1));
assign ac0_xcR =  (1'b0);
assign ac0_xcD = ((ac0 &  ~(r2))
       |  (ac0 & r3)
       |  (f0 & r0 & r2 &  ~(r3))
       |  ( ~(r0) & r1 & r2 &  ~(r3) & sl)
       |  ( ~(r0) &  ~(r1) & r2 &  ~(r3) & sr));
G_DEC ac0_B2LINST_10 ( .q(ac0_xcQ), .d(ac0_xcD), .clk(ac0_xcCLOCK), .e(1'b1), .c(ac0_xcR));
assign ac0 =  (ac0_xcQ);

assign ac1_xcCLOCK =  ((clock1));
assign ac1_xcR =  (1'b0);
assign ac1_xcD = ((ac1 &  ~(r2))
       |  (ac1 & r3)
       |  (f1 & r0 & r2 &  ~(r3))
       |  ( ~(r0) & r1 & r2 &  ~(r3) & sl)
       |  ( ~(r0) &  ~(r1) & r2 &  ~(r3) & sr));
G_DEC ac1_B2LINST_11 ( .q(ac1_xcQ), .d(ac1_xcD), .clk(ac1_xcCLOCK), .e(1'b1), .c(ac1_xcR));
assign ac1 =  (ac1_xcQ);

assign ac2_xcCLOCK =  ((clock1));
assign ac2_xcR =  (1'b0);
assign ac2_xcD = ((ac2 &  ~(r2))
       |  (ac2 & r3)
       |  (f2 & r0 & r2 &  ~(r3))
       |  ( ~(r0) & r1 & r2 &  ~(r3) & sl)
       |  ( ~(r0) &  ~(r1) & r2 &  ~(r3) & sr));
G_DEC ac2_B2LINST_12 ( .q(ac2_xcQ), .d(ac2_xcD), .clk(ac2_xcCLOCK), .e(1'b1), .c(ac2_xcR));
assign ac2 =  (ac2_xcQ);

assign pc0_xcCLOCK =  ((clock1));
assign pc0_xcR =  (1'b0);
assign pc0_xcD = ((pc0 &  ~(r0) & r1)
       |  (pc0 &  ~(r0) & r2)
       |  (pc0 &  ~(r0) &  ~(r3))
       |  (pc0 & r2 &  ~(r3))
       |  (f0 & r0 & r2 & r3)
       |  (pc0 & r0 &  ~(r2) & r3)
       |  (f0 &  ~(r0) &  ~(r1) &  ~(r2) & r3));
G_DEC pc0_B2LINST_13 ( .q(pc0_xcQ), .d(pc0_xcD), .clk(pc0_xcCLOCK), .e(1'b1), .c(pc0_xcR));
assign pc0 =  (pc0_xcQ);

assign pc1_xcCLOCK =  ((clock1));
assign pc1_xcR =  (1'b0);
assign pc1_xcD = ((pc1 &  ~(r0) & r1)
       |  (pc1 &  ~(r0) & r2)
       |  (pc1 &  ~(r0) &  ~(r3))
       |  (pc1 & r2 &  ~(r3))
       |  (f1 & r0 & r2 & r3)
       |  (pc1 & r0 &  ~(r2) & r3)
       |  (f1 &  ~(r0) &  ~(r1) &  ~(r2) & r3));
G_DEC pc1_B2LINST_14 ( .q(pc1_xcQ), .d(pc1_xcD), .clk(pc1_xcCLOCK), .e(1'b1), .c(pc1_xcR));
assign pc1 =  (pc1_xcQ);

assign pc2_xcCLOCK =  ((clock1));
assign pc2_xcR =  (1'b0);
assign pc2_xcD = ((pc2 &  ~(r0) & r1)
       |  (pc2 &  ~(r0) & r2)
       |  (pc2 &  ~(r0) &  ~(r3))
       |  (pc2 & r2 &  ~(r3))
       |  (f2 & r0 & r2 & r3)
       |  (pc2 & r0 &  ~(r2) & r3)
       |  (f2 &  ~(r0) &  ~(r1) &  ~(r2) & r3));
G_DEC pc2_B2LINST_15 ( .q(pc2_xcQ), .d(pc2_xcD), .clk(pc2_xcCLOCK), .e(1'b1), .c(pc2_xcR));
assign pc2 =  (pc2_xcQ);

assign f0 = ((AIM_0_RESULT2));

assign f1 = ((AIM_0_RESULT1));

assign f2 = ((AIM_0_RESULT0));

assign mux0 = ((inp0 & x0 &  ~(x1) & x2)
       |  (sw0 &  ~(x0) &  ~(x1) & x2)
       |  (pc0 & x0 & x1 &  ~(x2))
       |  (ac0 &  ~(x0) & x1 &  ~(x2))
       |  (ma0 & x0 &  ~(x1) &  ~(x2))
       |  (mb0 &  ~(x0) &  ~(x1) &  ~(x2)));

assign mux1 = ((inp1 & x0 &  ~(x1) & x2)
       |  (sw1 &  ~(x0) &  ~(x1) & x2)
       |  (pc1 & x0 & x1 &  ~(x2))
       |  (ac1 &  ~(x0) & x1 &  ~(x2))
       |  (ma1 & x0 &  ~(x1) &  ~(x2))
       |  (mb1 &  ~(x0) &  ~(x1) &  ~(x2)));

assign mux2 = ((inp2 & x0 &  ~(x1) & x2)
       |  (sw2 &  ~(x0) &  ~(x1) & x2)
       |  (pc2 & x0 & x1 &  ~(x2))
       |  (ac2 &  ~(x0) & x1 &  ~(x2))
       |  (ma2 & x0 &  ~(x1) &  ~(x2))
       |  (mb2 &  ~(x0) &  ~(x1) &  ~(x2)));

assign AIM_0_DATAA0 = ((mux2));

assign AIM_0_DATAA1 = ((mux1));

assign AIM_0_DATAA2 = ((mux0));

assign AIM_0_DATAB0 = ((ac2));

assign AIM_0_DATAB1 = ((ac1));

assign AIM_0_DATAB2 = ((ac0));

assign AIM_0_ADD_SUB = (1'b1);




endmodule