// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
module bm8l (ac06_bus_l, ac07_bus_l, ac08_bus_l, ac09_bus_l, ac10_bus_l, ac11_bus_l, b_init, bema, bf_enable_l, biop1, biop2, biop4, bma00, bma01, bma02, bma03, bma04, bma05, bma06, bma07, bma08, bma09, bma10, bma11, bmb00, bmb01, bmb02, bmb03, bmb03_l, bmb04, bmb04_l, bmb05, bmb05_l, bmb06, bmb06_l, bmb07, bmb07_l, bmb08, bmb08_l, bmb09, bmb10, bmb11, btp2, btp3, del1, del2, del3, del4, del5, del6, df_enable_l, done, e_or_f_set, ea0, ea0_l, ea1, ea1_l, ea2, ea2_l, ea_l, ema00_l, ema01_l, ema02_l, ema_l, ex_da0_l, ex_da1_l, ex_da2_l, field1, field1_l, inhibit, int_inhibit_l, jmp_or_jms, key_clr_l, key_df0, key_df1, key_df2_l, key_if0, key_if1, key_if2_l, key_load_l, load_sf_l, ma00_l, ma01_l, ma02_l, ma03_l, ma04_l, ma05_l, ma06_l, ma07_l, ma08_l, ma09_l, ma10_l, ma11_l, mem00, mem01, mem02, mem03, mem04, mem05, mem06, mem07, mem08, mem09, mem10, mem11, mem_done_l, mem_start, n_t_13x, n_t_14x, n_t_15x, n_t_17x, n_t_6x, not_fld0, power_ok, read_l, returnh, source, sp_cyc_next_l, strobe, strobe_l, write);
output ac06_bus_l;
output ac07_bus_l;
output ac08_bus_l;
output ac09_bus_l;
output ac10_bus_l;
output ac11_bus_l;
input b_init;
output bema;
input bf_enable_l;
input biop1;
input biop2;
input biop4;
input bma00;
input bma01;
input bma02;
input bma03;
input bma04;
input bma05;
input bma06;
input bma07;
input bma08;
input bma09;
input bma10;
input bma11;
input bmb00;
input bmb01;
input bmb02;
input bmb03;
inout bmb03_l;
input bmb04;
inout bmb04_l;
input bmb05;
inout bmb05_l;
input bmb06;
inout bmb06_l;
input bmb07;
inout bmb07_l;
input bmb08;
inout bmb08_l;
input bmb09;
input bmb10;
input bmb11;
input btp2;
input btp3;
input del1;
input del2;
input del3;
input del4;
input del5;
input del6;
input df_enable_l;
inout reg done;
input e_or_f_set;
inout reg ea0;
inout ea0_l;
inout reg ea1;
inout ea1_l;
inout reg ea2;
inout ea2_l;
output ea_l;
output ema00_l;
output ema01_l;
output ema02_l;
output ema_l;
input ex_da0_l;
input ex_da1_l;
input ex_da2_l;
output field1;
inout field1_l;
output inhibit;
output int_inhibit_l;
input jmp_or_jms;
input key_clr_l;
input key_df0;
input key_df1;
input key_df2_l;
input key_if0;
input key_if1;
input key_if2_l;
input key_load_l;
input load_sf_l;
output ma00_l;
output ma01_l;
output ma02_l;
output ma03_l;
output ma04_l;
output ma05_l;
output ma06_l;
output ma07_l;
output ma08_l;
output ma09_l;
output ma10_l;
output ma11_l;
output mem00;
output mem01;
output mem02;
output mem03;
output mem04;
output mem05;
output mem06;
output mem07;
output mem08;
output mem09;
output mem10;
output mem11;
output mem_done_l;
input mem_start;
input n_t_13x;
input n_t_14x;
input n_t_15x;
input n_t_17x;
output n_t_6x;
inout not_fld0;
input power_ok;
output read_l;
output returnh;
output source;
input sp_cyc_next_l;
output strobe;
output strobe_l;
inout write;

reg bf0_m;
reg bf1_m;
reg bf2_m;
reg df0_m;
reg df1_m;
reg df2_m;
reg done_m;
reg ea0_m;
reg ea1_m;
reg ea2_m;
reg eab0_m;
reg eab1_m;
reg eab2_m;
reg ib0_m;
reg ib1_m;
reg ib2_m;
reg if0_m;
reg if1_m;
reg if2_m;
reg inh_l_m;
reg inth_m;
reg n_t_66x_m;
reg n_t_67x_m;
reg n_t_68x_m;
reg n_t_69x_m;
reg n_t_70x_m;
reg n_t_71x_m;
reg n_t_72x_m;
reg n_t_73x_m;
reg n_t_74x_m;
reg n_t_75x_m;
reg n_t_76x_m;
reg n_t_77x_m;
reg read_m;
reg ret_l_m;
reg select_m;
reg sorc_l_m;
reg strob_l_m;
reg wrt_l_m;

reg n_t_68x;
reg n_t_69x;
reg n_t_70x;
reg n_t_71x;
reg n_t_66x;
reg n_t_67x;
reg n_t_72x;
reg n_t_73x;
reg n_t_74x;
reg n_t_75x;
reg n_t_76x;
reg n_t_77x;
reg eab0;
reg eab1;
reg eab2;
reg if0;
reg if1;
reg if2;
reg bf0;
reg bf1;
reg bf2;
reg ib0;
reg ib1;
reg ib2;
reg inth;
reg select;
reg df0;
reg df1;
reg df2;
reg sf0;
reg sf1;
reg sf2;
reg sf3;
reg sf4;
reg sf5;
reg read;
reg ret_l;
reg sorc_l;
reg strob_l;
reg wrt_l;
reg inh_l;
// internal nodes 
wire b_load_sf;
wire cdf_l;
wire cif_l;
wire del1_l;
wire del3wrt;
wire dfd0;
wire dfd1;
wire dfd2;
wire ea_ok;
wire ea_ok_l;
wire ead0;
wire ead1;
wire ead2;
wire ext_mem;
wire ibd0;
wire ibd1;
wire ibd2;
wire ibif_ena;
wire if_ena;
wire init_l;
wire load_df;
wire load_ib;
wire load_inh_l;
wire load_md_l;
wire n_t_16x;
wire n_t_18x;
wire n_t_19x;
wire n_t_21x;
wire n_t_22x;
wire n_t_23x;
wire n_t_25x;
wire n_t_26x;
wire n_t_27x;
wire n_t_28x;
wire n_t_29x;
wire n_t_2x;
wire n_t_31x;
wire n_t_32x;
wire n_t_33x;
wire n_t_34x;
wire n_t_35x;
wire n_t_36x;
wire n_t_37x;
wire n_t_38x;
wire n_t_39x;
wire n_t_3x;
wire n_t_40x;
wire n_t_41x;
wire n_t_42x;
wire n_t_45x;
wire n_t_47x;
wire n_t_48x;
wire n_t_49x;
wire n_t_4x;
wire n_t_50x;
wire n_t_51x;
wire n_t_52x;
wire n_t_55x;
wire n_t_56x;
wire n_t_57x;
wire n_t_58x;
wire n_t_59x;
wire n_t_5x;
wire n_t_60x;
wire n_t_61x;
wire n_t_62x;
wire n_t_63x;
wire n_t_64x;
wire n_t_65x;
wire rdf_l;
wire rib_l;
wire rif_l;
wire rmf_l;
wire save_field;
wire set_df0_l;
wire set_df1_l;
wire set_df2_l;
wire set_f0_l;
wire set_f1_l;
wire set_f2_l;
// code nodes 
// equations 
// a08: m117 
assign save_field = ~(~(bmb06 & bmb05_l & bmb04 & bmb03_l));
assign ext_mem = ~(~(bmb04 & bmb03_l));
assign rib_l = ~(biop4 & ext_mem & bmb07 & bmb08);
assign rif_l = ~(biop4 & ext_mem & bmb07 & bmb08_l);
assign rdf_l = ~(biop4 & ext_mem & bmb07_l & bmb08);
assign rmf_l = ~(biop4 & bmb07_l & bmb08_l & save_field);
// a09: m111 
// a10: m206 
always @(n_t_49x, n_t_51x, n_t_52x)
  if (~n_t_51x) begin
    n_t_68x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_68x_m <= ~n_t_52x;
  end
always @(n_t_49x, n_t_51x, n_t_68x_m)
  if (~n_t_51x) begin
    n_t_68x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_68x <= n_t_68x_m;
  end
always @(n_t_49x, n_t_51x, n_t_55x)
  if (~n_t_51x) begin
    n_t_69x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_69x_m <= ~n_t_55x;
  end
always @(n_t_49x, n_t_51x, n_t_69x_m)
  if (~n_t_51x) begin
    n_t_69x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_69x <= n_t_69x_m;
  end
always @(n_t_49x, n_t_51x, n_t_56x)
  if (~n_t_51x) begin
    n_t_70x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_70x_m <= ~n_t_56x;
  end
always @(n_t_49x, n_t_51x, n_t_70x_m)
  if (~n_t_51x) begin
    n_t_70x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_70x <= n_t_70x_m;
  end
always @(n_t_49x, n_t_51x, n_t_57x)
  if (~n_t_51x) begin
    n_t_71x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_71x_m <= ~n_t_57x;
  end
always @(n_t_49x, n_t_51x, n_t_71x_m)
  if (~n_t_51x) begin
    n_t_71x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_71x <= n_t_71x_m;
  end
always @(n_t_49x, n_t_51x, n_t_61x)
  if (~n_t_51x) begin
    n_t_66x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_66x_m <= ~n_t_61x;
  end
always @(n_t_49x, n_t_51x, n_t_66x_m)
  if (~n_t_51x) begin
    n_t_66x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_66x <= n_t_66x_m;
  end
always @(n_t_49x, n_t_51x, n_t_58x)
  if (~n_t_51x) begin
    n_t_67x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_67x_m <= ~n_t_58x;
  end
always @(n_t_49x, n_t_51x, n_t_67x_m)
  if (~n_t_51x) begin
    n_t_67x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_67x <= n_t_67x_m;
  end
// a11: empty 
// a12: empty 
// a13: empty 
// a14: m623 
// ac06_bus_l = !(if0 & !rif_l); 
// ac07_bus_l = !(if1 & !rif_l); 
// ac06_bus_l = !(df0 & !rdf_l); 
// ac07_bus_l = !(df1 & !rdf_l); 
// ac08_bus_l = !(!n_t_42x); 
// ac08_bus_l = !(!n_t_45x); 
// ac06_bus_l = !(sf0 & !rib_l); 
// ac09_bus_l = !(sf1 & !rib_l); 
// ac07_bus_l = !(sf2 & !rib_l); 
// ac10_bus_l = !(sf3 & !rib_l); 
// ac08_bus_l = !(sf4 & !rib_l); 
// ac11_bus_l = !(sf5 & !rib_l); 
// a15: empty 
// b08: m623 
// n_t_52x = !(bmb00 & !n_t_50x); 
// n_t_55x = !(bmb01 & !n_t_50x); 
// n_t_56x = !(bmb02 & !n_t_50x); 
// n_t_57x = !(!bmb03_l & !n_t_50x); 
// n_t_61x = !(!bmb04_l & !n_t_50x); 
// n_t_58x = !(!bmb05_l & !n_t_50x); 
// n_t_60x = !(!bmb06_l & !n_t_50x); 
// n_t_59x = !(!bmb07_l & !n_t_50x); 
// n_t_62x = !(!bmb08_l & !n_t_50x); 
// n_t_63x = !(bmb09 & !n_t_50x); 
// n_t_64x = !(bmb10 & !n_t_50x); 
// n_t_65x = !(bmb11 & !n_t_50x); 
// b09: m206 
always @(n_t_49x, n_t_51x, n_t_60x)
  if (~n_t_51x) begin
    n_t_72x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_72x_m <= ~n_t_60x;
  end
always @(n_t_49x, n_t_51x, n_t_72x_m)
  if (~n_t_51x) begin
    n_t_72x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_72x <= n_t_72x_m;
  end
always @(n_t_49x, n_t_51x, n_t_59x)
  if (~n_t_51x) begin
    n_t_73x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_73x_m <= ~n_t_59x;
  end
always @(n_t_49x, n_t_51x, n_t_73x_m)
  if (~n_t_51x) begin
    n_t_73x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_73x <= n_t_73x_m;
  end
always @(n_t_49x, n_t_51x, n_t_62x)
  if (~n_t_51x) begin
    n_t_74x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_74x_m <= ~n_t_62x;
  end
always @(n_t_49x, n_t_51x, n_t_74x_m)
  if (~n_t_51x) begin
    n_t_74x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_74x <= n_t_74x_m;
  end
always @(n_t_49x, n_t_51x, n_t_63x)
  if (~n_t_51x) begin
    n_t_75x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_75x_m <= ~n_t_63x;
  end
always @(n_t_49x, n_t_51x, n_t_75x_m)
  if (~n_t_51x) begin
    n_t_75x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_75x <= n_t_75x_m;
  end
always @(n_t_49x, n_t_51x, n_t_64x)
  if (~n_t_51x) begin
    n_t_76x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_76x_m <= ~n_t_64x;
  end
always @(n_t_49x, n_t_51x, n_t_76x_m)
  if (~n_t_51x) begin
    n_t_76x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_76x <= n_t_76x_m;
  end
always @(n_t_49x, n_t_51x, n_t_65x)
  if (~n_t_51x) begin
    n_t_77x_m <= 1'b1;
  end else
  if (~(n_t_49x)) begin
    n_t_77x_m <= ~n_t_65x;
  end
always @(n_t_49x, n_t_51x, n_t_77x_m)
  if (~n_t_51x) begin
    n_t_77x <= 1'b1;
  end else
  if (n_t_49x) begin
    n_t_77x <= n_t_77x_m;
  end
// b10: m111 
assign bmb03_l = ~bmb03;
assign bmb04_l = ~bmb04;
assign bmb05_l = ~bmb05;
assign bmb06_l = ~bmb06;
assign bmb07_l = ~bmb07;
assign bmb08_l = ~bmb08;
assign field1 = ~field1_l;
// b11: m623 
// mem00 = !(!n_t_68x & !n_t_48x); 
// mem01 = !(!n_t_69x & !n_t_48x); 
// mem02 = !(!n_t_70x & !n_t_48x); 
// mem03 = !(!n_t_71x & !n_t_48x); 
// mem04 = !(!n_t_66x & !n_t_48x); 
// mem05 = !(!n_t_67x & !n_t_48x); 
// mem06 = !(!n_t_72x & !n_t_48x); 
// mem07 = !(!n_t_73x & !n_t_48x); 
// mem08 = !(!n_t_74x & !n_t_48x); 
// mem09 = !(!n_t_75x & !n_t_48x); 
// mem10 = !(!n_t_76x & !n_t_48x); 
// mem11 = !(!n_t_77x & !n_t_48x); 
// b12: m627 
assign ema00_l = ~eab0;
assign ema01_l = ~eab1;
assign ema02_l = ~eab2;
assign ma00_l = ~bma00;
assign ma01_l = ~bma01;
assign ma02_l = ~bma02;
// b13: m627 
assign ma03_l = ~bma03;
assign ma04_l = ~bma04;
assign ma05_l = ~bma05;
assign ma06_l = ~bma06;
assign ma07_l = ~bma07;
assign ma08_l = ~bma08;
// b14: m627 
assign ma09_l = ~bma09;
assign ma10_l = ~bma10;
assign ma11_l = ~bma11;
assign n_t_50x = ~write;
assign n_t_48x = ~select;
assign b_load_sf = ~(load_sf_l & key_clr_l);
// b15: m623 
// strobe_l = !(!n_t_3x & select); 
// mem_done_l = !(done & select); 
// c08: m627 
assign returnh = ~ret_l;
assign source = ~sorc_l;
assign inhibit = ~inh_l;
assign write = ~wrt_l;
assign strobe = ~strob_l;
// c09: m115 
assign del1_l = ~del1;
assign ibif_ena = ~(~(bf_enable_l & sp_cyc_next_l & df_enable_l));
assign not_fld0 = ~(ea0_l & ea1_l & ea2_l);
assign n_t_3x = ~(del4 & read & read);
assign n_t_18x = ~(del2 & read & read);
assign n_t_5x = ~(del1 & write & write);
assign n_t_19x = ~(del5 & read & read);
assign load_inh_l = ~(e_or_f_set & jmp_or_jms & btp3);
// c10: m113 
assign if_ena = ~(e_or_f_set & jmp_or_jms);
assign n_t_28x = ~(ib2 & ~if_ena);
assign n_t_29x = ~(if2 & if_ena);
assign n_t_27x = ~(n_t_28x & n_t_29x);
assign n_t_21x = ~(df0 & ~df_enable_l);
assign ead0 = ~(n_t_21x & n_t_22x);
assign n_t_26x = ~(df1 & ~df_enable_l);
assign ead1 = ~(n_t_26x & n_t_25x);
assign n_t_34x = ~(df2 & ~df_enable_l);
assign ead2 = ~(n_t_34x & n_t_33x);
// c11: m113 
assign n_t_36x = ~(sf0 & bmb09);
assign n_t_31x = ~(bmb06 & ~bmb09);
assign ibd0 = ~(n_t_36x & n_t_31x);
assign n_t_35x = ~(sf1 & bmb09);
assign dfd0 = ~(n_t_31x & n_t_35x);
assign n_t_32x = ~(sf2 & bmb09);
assign n_t_38x = ~(bmb07 & ~bmb09);
assign ibd1 = ~(n_t_32x & n_t_38x);
assign n_t_37x = ~(sf3 & bmb09);
assign dfd1 = ~(n_t_38x & n_t_37x);
// c12: m113 
assign n_t_40x = ~(sf4 & bmb09);
assign n_t_39x = ~(bmb08 & ~bmb09);
assign ibd2 = ~(n_t_40x & n_t_39x);
assign n_t_41x = ~(sf5 & bmb09);
assign dfd2 = ~(n_t_39x & n_t_41x);
assign set_f0_l = ~(key_if0 & ~key_load_l);
assign set_df0_l = ~(key_df0 & ~key_load_l);
assign set_f1_l = ~(key_if1 & ~key_load_l);
assign set_df1_l = ~(key_df1 & ~key_load_l);
assign set_f2_l = ~(~key_if2_l & ~key_load_l);
// c13: m113 
assign n_t_42x = ~(if2 & ~rif_l);
assign n_t_45x = ~(df2 & ~rdf_l);
assign set_df2_l = ~(~key_df2_l & ~key_load_l);
assign n_t_2x = ~(~b_init & power_ok);
assign n_t_6x = ~(~mem_start & ~btp2);
assign cdf_l = ~(biop1 & ext_mem);
assign cif_l = ~(biop2 & ext_mem);
assign load_df = ~(rmf_l & cdf_l);
assign load_ib = ~(rmf_l & cif_l);
assign n_t_47x = ~(load_inh_l & key_clr_l);
// c14: m627 
assign n_t_49x = ~load_md_l;
assign n_t_51x = ~b_init;
assign init_l = ~n_t_2x;
assign ea_l = ~not_fld0;
assign ema_l = ~ea2;
assign bema = ~n_t_16x;
// c15: m206 
always @(mem_start, init_l, set_f0_l, ea0)
  if (~init_l) begin
    eab0_m <= 1'b0;
  end else
  if (~set_f0_l) begin
    eab0_m <= 1'b1;
  end else
  if (~(mem_start)) begin
    eab0_m <= ea0;
  end
always @(mem_start, init_l, set_f0_l, eab0_m)
  if (~init_l) begin
    eab0 <= 1'b0;
  end else
  if (~set_f0_l) begin
    eab0 <= 1'b1;
  end else
  if (mem_start) begin
    eab0 <= eab0_m;
  end
always @(mem_start, init_l, set_f1_l, ea1)
  if (~init_l) begin
    eab1_m <= 1'b0;
  end else
  if (~set_f1_l) begin
    eab1_m <= 1'b1;
  end else
  if (~(mem_start)) begin
    eab1_m <= ea1;
  end
always @(mem_start, init_l, set_f1_l, eab1_m)
  if (~init_l) begin
    eab1 <= 1'b0;
  end else
  if (~set_f1_l) begin
    eab1 <= 1'b1;
  end else
  if (mem_start) begin
    eab1 <= eab1_m;
  end
always @(mem_start, init_l, set_f2_l, ea2)
  if (~init_l) begin
    eab2_m <= 1'b0;
  end else
  if (~set_f2_l) begin
    eab2_m <= 1'b1;
  end else
  if (~(mem_start)) begin
    eab2_m <= ea2;
  end
always @(mem_start, init_l, set_f2_l, eab2_m)
  if (~init_l) begin
    eab2 <= 1'b0;
  end else
  if (~set_f2_l) begin
    eab2 <= 1'b1;
  end else
  if (mem_start) begin
    eab2 <= eab2_m;
  end
// c16: m115 
assign ea_ok_l = ~(not_fld0 & n_t_17x);
assign ea_ok = ~ea_ok_l;
assign field1_l = ~(ea0_l & ea1_l & ea2);
assign load_md_l = ~(del4 & read & read);
assign del3wrt = ~(~(del3 & write));
assign n_t_16x = ~(n_t_15x & n_t_14x & n_t_13x);
// d08: m111 
assign int_inhibit_l = ~inth;
// d09: m121 
assign n_t_4x = ~if_ena & ib0
                 | if_ena & if0;
assign n_t_23x = ib1 & ~if_ena
                  | if1 & if_ena;
assign n_t_22x = bf0 & ~bf_enable_l
                  | ibif_ena & ~n_t_4x;
assign n_t_25x = bf1 & ~bf_enable_l
                  | ibif_ena & ~n_t_23x;
assign n_t_33x = bf2 & ~bf_enable_l
                  | ibif_ena & n_t_27x;
// d10: m206 
always @(del3wrt, b_load_sf, set_f0_l, ead0)
  if (b_load_sf) begin
    ea0_m <= 1'b0;
  end else
  if (~set_f0_l) begin
    ea0_m <= 1'b1;
  end else
  if (~(del3wrt)) begin
    ea0_m <= ead0;
  end
always @(del3wrt, b_load_sf, set_f0_l, ea0_m)
  if (b_load_sf) begin
    ea0 <= 1'b0;
  end else
  if (~set_f0_l) begin
    ea0 <= 1'b1;
  end else
  if (del3wrt) begin
    ea0 <= ea0_m;
  end
assign ea0_l = ~ea0;
always @(del3wrt, b_load_sf, set_f1_l, ead1)
  if (b_load_sf) begin
    ea1_m <= 1'b0;
  end else
  if (~set_f1_l) begin
    ea1_m <= 1'b1;
  end else
  if (~(del3wrt)) begin
    ea1_m <= ead1;
  end
always @(del3wrt, b_load_sf, set_f1_l, ea1_m)
  if (b_load_sf) begin
    ea1 <= 1'b0;
  end else
  if (~set_f1_l) begin
    ea1 <= 1'b1;
  end else
  if (del3wrt) begin
    ea1 <= ea1_m;
  end
assign ea1_l = ~ea1;
always @(del3wrt, b_load_sf, set_f2_l, ead2)
  if (b_load_sf) begin
    ea2_m <= 1'b0;
  end else
  if (~set_f2_l) begin
    ea2_m <= 1'b1;
  end else
  if (~(del3wrt)) begin
    ea2_m <= ead2;
  end
always @(del3wrt, b_load_sf, set_f2_l, ea2_m)
  if (b_load_sf) begin
    ea2 <= 1'b0;
  end else
  if (~set_f2_l) begin
    ea2 <= 1'b1;
  end else
  if (del3wrt) begin
    ea2 <= ea2_m;
  end
assign ea2_l = ~ea2;
always @(load_inh_l, b_load_sf, set_f0_l, ib0)
  if (b_load_sf) begin
    if0_m <= 1'b0;
  end else
  if (~set_f0_l) begin
    if0_m <= 1'b1;
  end else
  if (~(~load_inh_l)) begin
    if0_m <= ib0;
  end
always @(load_inh_l, b_load_sf, set_f0_l, if0_m)
  if (b_load_sf) begin
    if0 <= 1'b0;
  end else
  if (~set_f0_l) begin
    if0 <= 1'b1;
  end else
  if (~load_inh_l) begin
    if0 <= if0_m;
  end
always @(load_inh_l, b_load_sf, set_f1_l, ib1)
  if (b_load_sf) begin
    if1_m <= 1'b0;
  end else
  if (~set_f1_l) begin
    if1_m <= 1'b1;
  end else
  if (~(~load_inh_l)) begin
    if1_m <= ib1;
  end
always @(load_inh_l, b_load_sf, set_f1_l, if1_m)
  if (b_load_sf) begin
    if1 <= 1'b0;
  end else
  if (~set_f1_l) begin
    if1 <= 1'b1;
  end else
  if (~load_inh_l) begin
    if1 <= if1_m;
  end
always @(load_inh_l, b_load_sf, set_f2_l, ib2)
  if (b_load_sf) begin
    if2_m <= 1'b0;
  end else
  if (~set_f2_l) begin
    if2_m <= 1'b1;
  end else
  if (~(~load_inh_l)) begin
    if2_m <= ib2;
  end
always @(load_inh_l, b_load_sf, set_f2_l, if2_m)
  if (b_load_sf) begin
    if2 <= 1'b0;
  end else
  if (~set_f2_l) begin
    if2 <= 1'b1;
  end else
  if (~load_inh_l) begin
    if2 <= if2_m;
  end
// d11: m206 
always @(del2, ex_da0_l, 1'b0)
  if (~ex_da0_l) begin
    bf0_m <= 1'b1;
  end else
  if (~(del2)) begin
    bf0_m <= 1'b0;
  end
always @(del2, ex_da0_l, bf0_m)
  if (~ex_da0_l) begin
    bf0 <= 1'b1;
  end else
  if (del2) begin
    bf0 <= bf0_m;
  end
always @(del2, ex_da1_l, 1'b0)
  if (~ex_da1_l) begin
    bf1_m <= 1'b1;
  end else
  if (~(del2)) begin
    bf1_m <= 1'b0;
  end
always @(del2, ex_da1_l, bf1_m)
  if (~ex_da1_l) begin
    bf1 <= 1'b1;
  end else
  if (del2) begin
    bf1 <= bf1_m;
  end
always @(del2, ex_da2_l, 1'b0)
  if (~ex_da2_l) begin
    bf2_m <= 1'b1;
  end else
  if (~(del2)) begin
    bf2_m <= 1'b0;
  end
always @(del2, ex_da2_l, bf2_m)
  if (~ex_da2_l) begin
    bf2 <= 1'b1;
  end else
  if (del2) begin
    bf2 <= bf2_m;
  end
always @(load_ib, b_load_sf, set_f0_l, ibd0)
  if (b_load_sf) begin
    ib0_m <= 1'b0;
  end else
  if (~set_f0_l) begin
    ib0_m <= 1'b1;
  end else
  if (~(load_ib)) begin
    ib0_m <= ibd0;
  end
always @(load_ib, b_load_sf, set_f0_l, ib0_m)
  if (b_load_sf) begin
    ib0 <= 1'b0;
  end else
  if (~set_f0_l) begin
    ib0 <= 1'b1;
  end else
  if (load_ib) begin
    ib0 <= ib0_m;
  end
always @(load_ib, b_load_sf, set_f1_l, ibd1)
  if (b_load_sf) begin
    ib1_m <= 1'b0;
  end else
  if (~set_f1_l) begin
    ib1_m <= 1'b1;
  end else
  if (~(load_ib)) begin
    ib1_m <= ibd1;
  end
always @(load_ib, b_load_sf, set_f1_l, ib1_m)
  if (b_load_sf) begin
    ib1 <= 1'b0;
  end else
  if (~set_f1_l) begin
    ib1 <= 1'b1;
  end else
  if (load_ib) begin
    ib1 <= ib1_m;
  end
always @(load_ib, b_load_sf, set_f2_l, ibd2)
  if (b_load_sf) begin
    ib2_m <= 1'b0;
  end else
  if (~set_f2_l) begin
    ib2_m <= 1'b1;
  end else
  if (~(load_ib)) begin
    ib2_m <= ibd2;
  end
always @(load_ib, b_load_sf, set_f2_l, ib2_m)
  if (b_load_sf) begin
    ib2 <= 1'b0;
  end else
  if (~set_f2_l) begin
    ib2 <= 1'b1;
  end else
  if (load_ib) begin
    ib2 <= ib2_m;
  end
// d12: m206 
always @(n_t_47x, init_l, load_ib, 1'b0)
  if (~init_l) begin
    inth_m <= 1'b0;
  end else
  if (load_ib) begin
    inth_m <= 1'b1;
  end else
  if (~(n_t_47x)) begin
    inth_m <= 1'b0;
  end
always @(n_t_47x, init_l, load_ib, inth_m)
  if (~init_l) begin
    inth <= 1'b0;
  end else
  if (load_ib) begin
    inth <= 1'b1;
  end else
  if (n_t_47x) begin
    inth <= inth_m;
  end
always @(mem_start, init_l, ea_ok)
  if (~init_l) begin
    select_m <= 1'b0;
  end else
  if (~(mem_start)) begin
    select_m <= ea_ok;
  end
always @(mem_start, init_l, select_m)
  if (~init_l) begin
    select <= 1'b0;
  end else
  if (mem_start) begin
    select <= select_m;
  end
always @(del6, init_l, n_t_19x, 1'b0)
  if (~init_l) begin
    done_m <= 1'b0;
  end else
  if (~n_t_19x) begin
    done_m <= 1'b1;
  end else
  if (~(del6)) begin
    done_m <= 1'b0;
  end
always @(del6, init_l, n_t_19x, done_m)
  if (~init_l) begin
    done <= 1'b0;
  end else
  if (~n_t_19x) begin
    done <= 1'b1;
  end else
  if (del6) begin
    done <= done_m;
  end
always @(load_df, b_load_sf, set_df0_l, dfd0)
  if (b_load_sf) begin
    df0_m <= 1'b0;
  end else
  if (~set_df0_l) begin
    df0_m <= 1'b1;
  end else
  if (~(load_df)) begin
    df0_m <= dfd0;
  end
always @(load_df, b_load_sf, set_df0_l, df0_m)
  if (b_load_sf) begin
    df0 <= 1'b0;
  end else
  if (~set_df0_l) begin
    df0 <= 1'b1;
  end else
  if (load_df) begin
    df0 <= df0_m;
  end
always @(load_df, b_load_sf, set_df1_l, dfd1)
  if (b_load_sf) begin
    df1_m <= 1'b0;
  end else
  if (~set_df1_l) begin
    df1_m <= 1'b1;
  end else
  if (~(load_df)) begin
    df1_m <= dfd1;
  end
always @(load_df, b_load_sf, set_df1_l, df1_m)
  if (b_load_sf) begin
    df1 <= 1'b0;
  end else
  if (~set_df1_l) begin
    df1 <= 1'b1;
  end else
  if (load_df) begin
    df1 <= df1_m;
  end
always @(load_df, b_load_sf, set_df2_l, dfd2)
  if (b_load_sf) begin
    df2_m <= 1'b0;
  end else
  if (~set_df2_l) begin
    df2_m <= 1'b1;
  end else
  if (~(load_df)) begin
    df2_m <= dfd2;
  end
always @(load_df, b_load_sf, set_df2_l, df2_m)
  if (b_load_sf) begin
    df2 <= 1'b0;
  end else
  if (~set_df2_l) begin
    df2 <= 1'b1;
  end else
  if (load_df) begin
    df2 <= df2_m;
  end
// d13: m206 
always @(posedge b_load_sf)
  if (b_load_sf) begin
    sf0 <= if0;
  end
always @(posedge b_load_sf)
  if (b_load_sf) begin
    sf1 <= df0;
  end
always @(posedge b_load_sf)
  if (b_load_sf) begin
    sf2 <= if1;
  end
always @(posedge b_load_sf)
  if (b_load_sf) begin
    sf3 <= df1;
  end
always @(posedge b_load_sf)
  if (b_load_sf) begin
    sf4 <= if2;
  end
always @(posedge b_load_sf)
  if (b_load_sf) begin
    sf5 <= df2;
  end
// d14: m206 
always @(btp2, init_l, mem_start, 1'b0)
  if (~init_l) begin
    read_m <= 1'b0;
  end else
  if (mem_start) begin
    read_m <= 1'b1;
  end else
  if (~(btp2)) begin
    read_m <= 1'b0;
  end
always @(btp2, init_l, mem_start, read_m)
  if (~init_l) begin
    read <= 1'b0;
  end else
  if (mem_start) begin
    read <= 1'b1;
  end else
  if (btp2) begin
    read <= read_m;
  end
assign read_l = ~read;
always @(del4, del1_l, init_l, 1'b1)
  if (~del1_l) begin
    ret_l_m <= 1'b0;
  end else
  if (~init_l) begin
    ret_l_m <= 1'b1;
  end else
  if (~(del4)) begin
    ret_l_m <= 1'b1;
  end
always @(del4, del1_l, init_l, ret_l_m)
  if (~del1_l) begin
    ret_l <= 1'b0;
  end else
  if (~init_l) begin
    ret_l <= 1'b1;
  end else
  if (del4) begin
    ret_l <= ret_l_m;
  end
always @(del3, del1_l, init_l, 1'b1)
  if (~del1_l) begin
    sorc_l_m <= 1'b0;
  end else
  if (~init_l) begin
    sorc_l_m <= 1'b1;
  end else
  if (~(del3)) begin
    sorc_l_m <= 1'b1;
  end
always @(del3, del1_l, init_l, sorc_l_m)
  if (~del1_l) begin
    sorc_l <= 1'b0;
  end else
  if (~init_l) begin
    sorc_l <= 1'b1;
  end else
  if (del3) begin
    sorc_l <= sorc_l_m;
  end
always @(del3, n_t_18x, init_l, 1'b1)
  if (~n_t_18x) begin
    strob_l_m <= 1'b0;
  end else
  if (~init_l) begin
    strob_l_m <= 1'b1;
  end else
  if (~(del3)) begin
    strob_l_m <= 1'b1;
  end
always @(del3, n_t_18x, init_l, strob_l_m)
  if (~n_t_18x) begin
    strob_l <= 1'b0;
  end else
  if (~init_l) begin
    strob_l <= 1'b1;
  end else
  if (del3) begin
    strob_l <= strob_l_m;
  end
always @(del5, btp2, init_l, 1'b1)
  if (~btp2) begin
    wrt_l_m <= 1'b0;
  end else
  if (~init_l) begin
    wrt_l_m <= 1'b1;
  end else
  if (~(del5)) begin
    wrt_l_m <= 1'b1;
  end
always @(del5, btp2, init_l, wrt_l_m)
  if (~btp2) begin
    wrt_l <= 1'b0;
  end else
  if (~init_l) begin
    wrt_l <= 1'b1;
  end else
  if (del5) begin
    wrt_l <= wrt_l_m;
  end
always @(del4, n_t_5x, init_l, 1'b1)
  if (~n_t_5x) begin
    inh_l_m <= 1'b0;
  end else
  if (~init_l) begin
    inh_l_m <= 1'b1;
  end else
  if (~(del4)) begin
    inh_l_m <= 1'b1;
  end
always @(del4, n_t_5x, init_l, inh_l_m)
  if (~n_t_5x) begin
    inh_l <= 1'b0;
  end else
  if (~init_l) begin
    inh_l <= 1'b1;
  end else
  if (del4) begin
    inh_l <= inh_l_m;
  end
// open collector 'wire-or's 
assign ac06_bus_l = (if0 & ~rif_l)
                     | (df0 & ~rdf_l)
                     | (sf0 & ~rib_l)? 1'b0: 1'bz;
assign ac07_bus_l = (if1 & ~rif_l)
                     | (df1 & ~rdf_l)
                     | (sf2 & ~rib_l)? 1'b0: 1'bz;
assign ac08_bus_l = (~n_t_42x)
                     | (~n_t_45x)
                     | (sf4 & ~rib_l)? 1'b0: 1'bz;
assign ac09_bus_l = (sf1 & ~rib_l)? 1'b0: 1'bz;
assign ac10_bus_l = (sf3 & ~rib_l)? 1'b0: 1'bz;
assign ac11_bus_l = (sf5 & ~rib_l)? 1'b0: 1'bz;
assign mem00 = (~n_t_68x & ~n_t_48x)? 1'b0: 1'bz;
assign mem01 = (~n_t_69x & ~n_t_48x)? 1'b0: 1'bz;
assign mem02 = (~n_t_70x & ~n_t_48x)? 1'b0: 1'bz;
assign mem03 = (~n_t_71x & ~n_t_48x)? 1'b0: 1'bz;
assign mem04 = (~n_t_66x & ~n_t_48x)? 1'b0: 1'bz;
assign mem05 = (~n_t_67x & ~n_t_48x)? 1'b0: 1'bz;
assign mem06 = (~n_t_72x & ~n_t_48x)? 1'b0: 1'bz;
assign mem07 = (~n_t_73x & ~n_t_48x)? 1'b0: 1'bz;
assign mem08 = (~n_t_74x & ~n_t_48x)? 1'b0: 1'bz;
assign mem09 = (~n_t_75x & ~n_t_48x)? 1'b0: 1'bz;
assign mem10 = (~n_t_76x & ~n_t_48x)? 1'b0: 1'bz;
assign mem11 = (~n_t_77x & ~n_t_48x)? 1'b0: 1'bz;
assign mem_done_l = (done & select)? 1'b0: 1'bz;
assign n_t_52x = ~((bmb00 & ~n_t_50x));
assign n_t_55x = ~((bmb01 & ~n_t_50x));
assign n_t_56x = ~((bmb02 & ~n_t_50x));
assign n_t_57x = ~((~bmb03_l & ~n_t_50x));
assign n_t_58x = ~((~bmb05_l & ~n_t_50x));
assign n_t_59x = ~((~bmb07_l & ~n_t_50x));
assign n_t_60x = ~((~bmb06_l & ~n_t_50x));
assign n_t_61x = ~((~bmb04_l & ~n_t_50x));
assign n_t_62x = ~((~bmb08_l & ~n_t_50x));
assign n_t_63x = ~((bmb09 & ~n_t_50x));
assign n_t_64x = ~((bmb10 & ~n_t_50x));
assign n_t_65x = ~((bmb11 & ~n_t_50x));
assign strobe_l = (~n_t_3x & select)? 1'b0: 1'bz;
endmodule