// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
// internal nodes 
// code nodes 
// equations 
// c1: cpol_use 
// c2: cpol_use 
// c3: cpol_use 
// c4: cpol_use 
// c5: cpol_use 
// c6: cpol_use 
// c7: cpol_use 
// c8: cpol_use 
// c9: cpol_use 
// e1: sn7453 
// aj1 = !(shift_r1 & adder1
//        # no_shift & adder2
//        # adder3 & shift_l1
//        # shift_r2 & adder0); 
// n_t_10x = !aj1; 
// e2: sn7453 
// ak2 = !(adder4 & shift_l1
//        # adder3 & no_shift
//        # adder2 & shift_r1
//        # shift_r2 & adder1); 
// n_t_9x = !ak2; 
// e3: sn7460 
// aj1 = !(!mb2_h & and_h); 
// n_t_10x = !aj1; 
// aj1 = !(adder4 & shift_l2); 
// n_t_10x = !aj1; 
// e4: sn7474 
module m220c (ac2_h, ac2_l, ac3_h, ac3_l, ac_enabl, ac_enabl_l, adder0, adder1, adder2, adder3, adder4, adder5, aj1, ak1, ak2, an2, and_h, ar1, as1, as2, at2, au1, au2, bb2, be2, br2, bu1, bv1, bv2, c0, c2, da2, da_enabl, data2, data3, data_enabl, io2, io3, io_enabl, ma2_h, ma2_l, ma3_h, ma3_l, ma_enabl, mem2, mem_enabl, mq2_h, mq3_h, mq_enabl, no_shift, pc2_h, pc2_l, pc3_h, pc3_l, pc_enabl, sc2, sc3, sc_enabl, shift_l1, shift_l2, shift_r1, shift_r2, sr2, sr3, sr_enabl, tt_shift_l);
inout reg ac2_h;
inout ac2_l;
inout reg ac3_h;
inout ac3_l;
input ac_enabl;
input ac_enabl_l;
input adder0;
input adder1;
inout adder2;
inout adder3;
input adder4;
input adder5;
inout aj1;
input ak1;
inout ak2;
input an2;
input and_h;
input ar1;
output as1;
output as2;
output at2;
input au1;
output au2;
input bb2;
input be2;
input br2;
input bu1;
input bv1;
input bv2;
input c0;
output c2;
input da2;
input da_enabl;
input data2;
input data3;
input data_enabl;
input io2;
input io3;
input io_enabl;
inout reg ma2_h;
output ma2_l;
inout reg ma3_h;
output ma3_l;
input ma_enabl;
input mem2;
input mem_enabl;
input mq2_h;
input mq3_h;
input mq_enabl;
input no_shift;
inout reg pc2_h;
output pc2_l;
inout reg pc3_h;
output pc3_l;
input pc_enabl;
input sc2;
input sc3;
input sc_enabl;
input shift_l1;
input shift_l2;
input shift_r1;
input shift_r2;
input sr2;
input sr3;
input sr_enabl;
input tt_shift_l;

wire  tt_shift = !tt_shift_l;

reg mb2_h;
reg mb3_h;
wire n_t_10x;
wire n_t_9x;
always @(posedge ak1)
  if (ak1) begin
    ma2_h <= aj1;
  end
assign ma2_l = ~ma2_h;
always @(posedge ak1)
  if (ak1) begin
    ma3_h <= ak2;
  end
assign ma3_l = ~ma3_h;
// e5: sn7460 
// ak2 = !(!mb3_h & and_h); 
// n_t_9x = !ak2; 
// ak2 = !(adder5 & shift_l2); 
// n_t_9x = !ak2; 
// e6: sn7460 
// aj1 = !(bb2 & tt_shift); 
// n_t_10x = !aj1; 
// ak2 = !(adder3 & tt_shift); 
// n_t_9x = !ak2; 
// e7: sn7440 
assign as2 = mb3_h;
assign as1 = ~mb3_h;
// e8: sn7474 
always @(posedge ar1)
  if (ar1) begin
    mb2_h <= aj1;
  end
always @(posedge ar1)
  if (ar1) begin
    mb3_h <= ak2;
  end
// e9: sn7474 
always @(posedge an2)
  if (an2) begin
    pc2_h <= aj1;
  end
assign pc2_l = ~pc2_h;
always @(posedge an2)
  if (an2) begin
    pc3_h <= ak2;
  end
assign pc3_l = ~pc3_h;
// e10: sn7474 
always @(posedge au1)
  if (au1) begin
    ac2_h <= aj1;
  end
assign ac2_l = ~ac2_h;
always @(posedge au1)
  if (au1) begin
    ac3_h <= ak2;
  end
assign ac3_l = ~ac3_h;
// e11: sn7440 
assign au2 = ~mb2_h;
assign at2 = mb2_h;
// e12: sn7453 
// n_t_4x = !(be2
//       # ac3_h & ac_enabl
//       # ac3_l & ac_enabl_l
//       # mq3_h & mq_enabl); 
// n_t_2x = !n_t_4x; 
// e13: sn7482 
assign adder3 = c0
                 ^ n_t_4x
                 ^ gdollar_3;
wire gdollar_0 = c0 & n_t_4x
                    | n_t_4x & gdollar_3
                    | c0 & gdollar_3;
assign adder2 = gdollar_1
                 ^ n_t_6x
                 ^ gdollar_0;
assign c2 = gdollar_0 & gdollar_1
             | gdollar_1 & n_t_6x
             | n_t_6x & gdollar_0;
// e14: sn7453 
// n_t_6x = !(sr_enabl & sr2
//       # sc2 & sc_enabl
//       # data2 & data_enabl
//       # io2 & io_enabl); 
// n_t_7x = !n_t_6x; 
// e15: sn7453 
// n_t_4x = !(sr_enabl & sr3
//       # sc3 & sc_enabl
//       # data3 & data_enabl
//       # io3 & io_enabl); 
// n_t_2x = !n_t_4x; 
// e16: sn7453 
// n_t_6x = !(ac2_h & ac_enabl
//       # ac2_l & ac_enabl_l
//       # mq2_h & mq_enabl); 
// n_t_7x = !n_t_6x; 
// e17: sn7453 
// gdollar_1 = !(ma_enabl & ma2_h
//          # pc2_h & pc_enabl
//          # mem2 & mem_enabl
//          # da2 & da_enabl); 
// !gdollar_1 = !gdollar_1; 
// e18: sn7453 
// gdollar_3 = !(br2 & ma3_h
//          # pc3_h & pc_enabl
//          # bv2 & bv1
//          # bu1 & da_enabl); 
// !gdollar_3 = !gdollar_3; 
// open collector 'wire-or's 
wire gdollar_1 = ~((ma_enabl & ma2_h
                       | pc2_h & pc_enabl
                       | mem2 & mem_enabl
                       | da2 & da_enabl));
wire gdollar_3 = ~((br2 & ma3_h
                       | pc3_h & pc_enabl
                       | bv2 & bv1
                       | bu1 & da_enabl));
//assign n_t_10x = ~aj1;
assign ak2 = ~((adder4 & shift_l1
                 | adder3 & no_shift
                 | adder2 & shift_r1
                 | shift_r2 & adder1)
                | (~mb3_h & and_h)
                | (adder5 & shift_l2)
                | (adder3 & tt_shift));
assign aj1 = ~((shift_r1 & adder1
                 | no_shift & adder2
                 | adder3 & shift_l1
                 | shift_r2 & adder0)
                | (~mb2_h & and_h)
                | (adder4 & shift_l2)
                | (bb2 & tt_shift));
//assign n_t_2x = ~n_t_4x;
wire n_t_4x = ~((be2
                    | ac3_h & ac_enabl
                    | ac3_l & ac_enabl_l
                    | mq3_h & mq_enabl)
                   | (sr_enabl & sr3
                      | sc3 & sc_enabl
                      | data3 & data_enabl
                      | io3 & io_enabl));
wire n_t_6x = ~((sr_enabl & sr2
                    | sc2 & sc_enabl
                    | data2 & data_enabl
                    | io2 & io_enabl)
                   | (ac2_h & ac_enabl
                      | ac2_l & ac_enabl_l
                      | mq2_h & mq_enabl));
//assign n_t_7x = ~n_t_6x;
//assign n_t_9x = ~ak2;
endmodule