// This file is generated by topld.pl 
// Please don't edit it. 
// Input Pins 
// Output Pins 
module M221D (adder1, adder4, carry_in, data_add, data_add_2, data_add_3, enable_ac, enable_ac_l, enable_ac_r, enable_bcl, enable_bse, enable_ma2, enable_ma3, enable_mb2, enable_mb3, enable_mem, enable_mq, enable_pc, enable_rsw, load_ac, load_ma, load_mb, load_pc, ls_msc2, ls_msc3, lsw, lsw2, lsw3, mem2, mem3, mq2, mq3, no_rot, rot_left, rot_right, rs_msc2, rs_msc3, rsw2, rsw3, a=b, adder2, adder3, addr_match, carry_ok_l, carry_out_2, ma2_h, ma2_l, ma3_h, ma3_l, n_t_11x, n_t_12x, n_t_13x, n_t_14x, n_t_15x, n_t_16x, n_t_17x, n_t_18x, pc2_l, pc3_l, ps_2, ps_3, ps_left_2, ps_left_3, reg_bus2, reg_bus3);
input adder1;
input adder4;
input carry_in;
input data_add;
input data_add_2;
input data_add_3;
input enable_ac;
input enable_ac_l;
input enable_ac_r;
input enable_bcl;
input enable_bse;
input enable_ma2;
input enable_ma3;
input enable_mb2;
input enable_mb3;
input enable_mem;
input enable_mq;
input enable_pc;
input enable_rsw;
input load_ac;
input load_ma;
input load_mb;
input load_pc;
input ls_msc2;
input ls_msc3;
input lsw;
input lsw2;
input lsw3;
input mem2;
input mem3;
input mq2;
input mq3;
input no_rot;
input rot_left;
input rot_right;
input rs_msc2;
input rs_msc3;
input rsw2;
input rsw3;
output a=b;
inout adder2;
inout adder3;
inout addr_match;
output carry_ok_l;
output carry_out_2;
inout reg ma2_h;
inout ma2_l;
inout reg ma3_h;
inout ma3_l;
output n_t_11x;
output n_t_12x;
output n_t_13x;
output n_t_14x;
output n_t_15x;
output n_t_16x;
output n_t_17x;
output n_t_18x;
output pc2_l;
output pc3_l;
inout ps_2;
inout ps_3;
inout ps_left_2;
inout ps_left_3;
inout reg_bus2;
inout reg_bus3;


reg ac3_h;
reg ac2_h;
reg mb3_h;
reg mb2_h;
reg pc3_h;
reg pc2_h;
// Internal nodes 
wire n_t_2x;
wire n_t_5x;
// Code nodes 
// Equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// e1: sn7453 
// ps_2 = !(ac2_h & enable_ac_r
//       # rs_msc2
//       # rsw2 & enable_rsw
//       # enable_pc & pc2_h); 
// n_t_4x = !ps_2; 
// e2: sn7453 
// reg_bus2 = !(rot_right & adder1
//          # rot_left & adder3
//          # no_rot & adder2
//          # !lsw2 & lsw); 
// !reg_bus2 = !reg_bus2; 
// e3: sn7453 
// addr_match = !(lsw2 & ma2_l
//          # lsw3 & ma3_l
//          # !lsw3 & ma3_h
//          # !lsw2 & ma2_h); 
// !addr_match = !addr_match; 
// e4: sn7453 
// ps_2 = !(data_add_2 & data_add
//       # mb2_h & enable_mb2
//       # ma2_h & enable_ma2
//       # enable_mem & mem2); 
// n_t_4x = !ps_2; 
// e5: sn7482 
assign adder3 = carry_in
                 ^ ps_left_3
                 ^ ps_3;
assign gdollar_4 = carry_in & ps_left_3
                    | ps_left_3 & ps_3
                    | carry_in & ps_3;
assign adder2 = ps_2
                 ^ ps_left_2
                 ^ gdollar_4;
assign carry_out_2 = gdollar_4 & ps_2
                      | ps_2 & ps_left_2
                      | ps_left_2 & gdollar_4;
// e6: sn7453 
// reg_bus3 = !(adder2 & rot_right
//          # adder4 & rot_left
//          # lsw & !lsw3
//          # no_rot & adder3); 
// !reg_bus3 = !reg_bus3; 
// e7: sn7453 
// ps_left_2 = !(enable_mq & mq2
//       # ls_msc2
//       # enable_ac_l & ac2_h
//       # enable_ac & !ac2_h); 
// n_t_5x = !ps_left_2; 
// e8: sn7474 
always @(posedge load_ac)
  if (load_ac) begin
    ac3_h <= reg_bus3;
  end
always @(posedge load_ac)
  if (load_ac) begin
    ac2_h <= reg_bus2;
  end
// e9: sn7400 
// e10: sn7460 
// ps_left_2 = !(!mb2_h & enable_bcl & enable_bcl & ac2_h); 
// n_t_5x = !ps_left_2; 
// ps_left_3 = !(enable_bcl & !mb3_h & ac3_h); 
// n_t_2x = !ps_left_3; 
// e11: sn7474 
always @(posedge load_mb)
  if (load_mb) begin
    mb3_h <= reg_bus3;
  end
always @(posedge load_mb)
  if (load_mb) begin
    mb2_h <= reg_bus2;
  end
// e12: sn7453 
// carry_ok_l = !(!ac3_h & ps_3
//          # ac2_h & !ps_2
//          # !ac2_h & ps_2
//          # !ps_3 & ac3_h); 
// !carry_ok_l = !carry_ok_l; 
// e13: sn7460 
// ps_left_2 = !(mb2_h & enable_bse & enable_bse & !ac2_h); 
// n_t_5x = !ps_left_2; 
// ps_left_3 = !(enable_bse & !ac3_h & mb3_h); 
// n_t_2x = !ps_left_3; 
// e14: sn7474 
always @(posedge load_pc)
  if (load_pc) begin
    pc3_h <= reg_bus3;
  end
assign pc3_l = ~pc3_h;
always @(posedge load_pc)
  if (load_pc) begin
    pc2_h <= reg_bus2;
  end
assign pc2_l = ~pc2_h;
// e15: sn7453 
// gdollar_9 = !(!ac3_h & mb3_h
//          # ac2_h & !mb2_h
//          # !ac2_h & mb2_h
//          # !mb3_h & ac3_h); 
// !gdollar_9 = !gdollar_9; 
assign a=b = gdollar_9;
// e16: sn7453 
// ps_left_3 = !(enable_mq & mq3
//       # ls_msc3
//       # enable_ac_l & ac3_h
//       # enable_ac & !ac3_h); 
// n_t_2x = !ps_left_3; 
// e17: sn7474 
always @(posedge load_ma)
  if (load_ma) begin
    ma3_h <= reg_bus3;
  end
assign ma3_l = ~ma3_h;
always @(posedge load_ma)
  if (load_ma) begin
    ma2_h <= reg_bus2;
  end
assign ma2_l = ~ma2_h;
// e18: sn74h00 
assign n_t_13x = ac3_h;
assign n_t_12x = ~ac2_h;
assign n_t_14x = ~ac3_h;
assign n_t_11x = ac2_h;
// e19: sn7453 
// ps_3 = !(data_add_3 & data_add
//       # mb3_h & enable_mb3
//       # ma3_h & enable_ma3
//       # enable_mem & mem3); 
// n_t_7x = !ps_3; 
// e20: sn7453 
// ps_3 = !(ac3_h & enable_ac_r
//       # rs_msc3
//       # rsw3 & enable_rsw
//       # enable_pc & pc3_h); 
// n_t_7x = !ps_3; 
// e21: sn74h00 
assign n_t_18x = ~mb3_h;
assign n_t_17x = mb3_h;
assign n_t_15x = mb2_h;
assign n_t_16x = ~mb2_h;
// r1: r_us_ 
// r2: r_us_ 
// r3: r_us_ 
// r4: r_us_ 
// r5: r_us_ 
// r6: r_us_ 
// r7: r_us_ 
// r8: r_us_ 
// r9: r_us_ 
// r10: r_us_ 
// r11: r_us_ 
// r12: r_us_ 
// r13: r_us_ 
// r14: r_us_ 
// Open collector 'wire-or's 
assign reg_bus2 = ~((rot_right & adder1
                      | rot_left & adder3
                      | no_rot & adder2
                      | ~lsw2 & lsw));
assign addr_match = ~((lsw2 & ma2_l
                        | lsw3 & ma3_l
                        | ~lsw3 & ma3_h
                        | ~lsw2 & ma2_h));
assign reg_bus3 = ~((adder2 & rot_right
                      | adder4 & rot_left
                      | lsw & ~lsw3
                      | no_rot & adder3));
assign carry_ok_l = ~((~ac3_h & ps_3
                        | ac2_h & ~ps_2
                        | ~ac2_h & ps_2
                        | ~ps_3 & ac3_h));
assign gdollar_9 = ~((~ac3_h & mb3_h
                       | ac2_h & ~mb2_h
                       | ~ac2_h & mb2_h
                       | ~mb3_h & ac3_h));
assign ps_left_3 = ~((enable_bcl & ~mb3_h & ac3_h)
                      | (enable_bse & ~ac3_h & mb3_h)
                      | (enable_mq & mq3
                         | ls_msc3
                         | enable_ac_l & ac3_h
                         | enable_ac & ~ac3_h));
assign n_t_2x = ~ps_left_3;
assign ps_2 = ~ac2_h & enable_ac_r
                  | rs_msc2
                  | rsw2 & enable_rsw
                  | enable_pc & pc2_h
                 | data_add_2 & data_add
                    | mb2_h & enable_mb2
                    | ma2_h & enable_ma2
                    | enable_mem & mem2;
assign n_t_4x = ~ps_2;
assign n_t_5x = ~ps_left_2;
assign ps_left_2 = ~((enable_mq & mq2
                       | ls_msc2
                       | enable_ac_l & ac2_h
                       | enable_ac & ~ac2_h)
                      | (~mb2_h & enable_bcl & enable_bcl & ac2_h)
                      | (mb2_h & enable_bse & enable_bse & ~ac2_h));
assign n_t_7x = ~ps_3;
assign ps_3 = ~data_add_3 & data_add
                  | mb3_h & enable_mb3
                  | ma3_h & enable_ma3
                  | enable_mem & mem3
                 | ac3_h & enable_ac_r
                    | rs_msc3
                    | rsw3 & enable_rsw
                    | enable_pc & pc3_h;
endmodule