// This file is generated by topld.pl 
// Please don't edit it. 
// Input Pins 
// Output Pins 
module M8341 (ac0, ac0_ne_ac1, ac1, ac2_8_0, ac4_11_0, ac_0, ad0_low, carry_out_low, clock, dad_or_dst, dad_or_dst_low, div_12_l, e, eir2, eir3, fetch, gtf_or_ind, init, last_step_l, link, modeb, mq0_low, mq10_low, mq11_low, mq_0, msir_disable, next_loc, rom_11_l, rom_12_l, rom_13_l, rom_14_l, rom_15_l, rom_17_l, rom_22_l, rom_24_l, rtf, sc_0_low, sgt_low, tp1, tp2, tp3, ts2, ts3, ts4, ac_load_low, ac_to_bus_low, ac_to_mq_ena_low, ad_lk_low, c0, carry_in, data1, data_f, data_t, en0, en1, en2, incr_sc, left_low, link_data, link_load, md_disable, mq_data_low, mq_load, mq_to_bus_low, not_last_xfer, restart, right_low, shl_ena_low, skip, tp, tp2_d);
input ac0;
input ac0_ne_ac1;
input ac1;
input ac2_8_0;
input ac4_11_0;
input ac_0;
input ad0_low;
input carry_out_low;
input clock;
input dad_or_dst;
input dad_or_dst_low;
input div_12_l;
input e;
input eir2;
input eir3;
input fetch;
input gtf_or_ind;
input init;
input last_step_l;
input link;
input modeb;
input mq0_low;
input mq10_low;
input mq11_low;
input mq_0;
input msir_disable;
input next_loc;
input rom_11_l;
input rom_12_l;
input rom_13_l;
input rom_14_l;
input rom_15_l;
input rom_17_l;
input rom_22_l;
input rom_24_l;
input rtf;
input sc_0_low;
input sgt_low;
input tp1;
input tp2;
input tp3;
input ts2;
input ts3;
input ts4;
inout ac_load_low;
output ac_to_bus_low;
inout ac_to_mq_ena_low;
output ad_lk_low;
output c0;
output carry_in;
inout data1;
output data_f;
output data_t;
output en0;
output en1;
inout en2;
output incr_sc;
output left_low;
output link_data;
output link_load;
output md_disable;
output mq_data_low;
output mq_load;
output mq_to_bus_low;
output not_last_xfer;
output restart;
output right_low;
output shl_ena_low;
output skip;
inout reg tp;
inout reg tp2_d;

reg eae_on_m;
reg n_t_13x_m;
reg n_t_42x_m;
reg n_t_60x_m;
reg n_t_69x_m;
reg n_t_84x_m;
reg tp_m;

reg n_t_23x;
reg n_t_65x;
reg n_t_22x;
reg n_t_42x;
reg n_t_84x;
reg n_t_69x;
reg eae_on;
reg n_t_60x;
reg n_t_13x;
// Internal nodes 
wire ac2_mq11_0;
wire bac0;
wire dcm_or_dpic_low;
wire dvi;
wire dvi_and_ts3;
wire etp;
wire etp_or_tp3;
wire last_dvi_low;
wire lp_asr_or_lsr_rp_and_eae_on_low;
wire lp_dcm_or_dpic_or_sam_rp_and_ts3;
wire lp_shl_or_norms_rp_and_eae_on_low;
wire mq0_gt_ac0;
wire mq_ge_ac;
wire muy_and_eae_on_low;
wire n_t_15x;
wire n_t_18x;
wire n_t_19x;
wire n_t_21x;
wire n_t_24x;
wire n_t_27x;
wire n_t_28x;
wire n_t_33x;
wire n_t_34x;
wire n_t_38x;
wire n_t_3x;
wire n_t_40x;
wire n_t_43x;
wire n_t_44x;
wire n_t_46x;
wire n_t_49x;
wire n_t_4x;
wire n_t_52x;
wire n_t_53x;
wire n_t_56x;
wire n_t_5x;
wire n_t_61x;
wire n_t_63x;
wire n_t_64x;
wire n_t_66x;
wire n_t_67x;
wire n_t_68x;
wire n_t_70x;
wire n_t_73x;
wire n_t_74x;
wire n_t_76x;
wire n_t_77x;
wire n_t_82x;
wire n_t_85x;
wire n_t_92x;
wire normal_dvi_low;
wire norms_or_shl_or_asr_or_lsr;
wire sam_low;
wire shift_ok;
// Code nodes 
// Equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: c_us 
// c25: c_us 
// c26: c_us 
// c27: c_us 
// c28: c_us 
// c29: c_us 
// c30: c_us 
// c31: c_us 
// c32: c_us 
// c33: cpol_use 
// c34: cpol_use 
// c35: cpol_use 
// e1: sn74h74 
always @(negedge clock)
  if (~clock) begin
    n_t_23x <= n_t_22x;
  end
always @(clock, eae_on, n_t_23x)
  if (~eae_on) begin
    tp_m <= 1'b1;
  end else
  if (~(~clock)) begin
    tp_m <= ~n_t_23x;
  end
always @(clock, eae_on, tp_m)
  if (~eae_on) begin
    tp <= 1'b1;
  end else
  if (~clock) begin
    tp <= tp_m;
  end
// e2: sn7410 
assign n_t_19x = ~n_t_27x & n_t_18x & ac2_mq11_0;
assign n_t_76x = ~tp & eae_on & rom_12_l;
assign n_t_63x = ~(eae_on & tp & ~rom_12_l);
// e3: sp380n 
assign n_t_53x = ~link
                    | rom_13_l;
// e4: sn7404 
// e5: sn74h74 
always @(negedge clock)
  if (~clock) begin
    n_t_65x <= n_t_63x;
  end
always @(negedge clock)
  if (~clock) begin
    n_t_22x <= n_t_21x;
  end
// e6: sn7400 
assign n_t_38x = ~sc_0_low & mq10_low;
assign n_t_73x = ~n_t_4x & tp3;
assign n_t_21x = ~n_t_65x & n_t_76x;
assign n_t_82x = ~sc_0_low & n_t_85x;
// e7: sn7402 
assign n_t_27x = ~ac1
                    | n_t_15x;
assign n_t_49x = ~rom_13_l
                    | carry_out_low;
assign n_t_18x = ~n_t_15x
                    | dad_or_dst;
assign n_t_28x = ~n_t_27x
                    | n_t_18x;
// e8: sn74h53 
// shift_ok = !(ac0_ne_ac1 & n_t_18x
//          # modeb & !last_step_l & norms_or_shl_or_asr_or_lsr
//          # ac2_mq11_0 & !n_t_28x); 
// !shift_ok = !shift_ok; 
// e9: sn7402 
assign etp_or_tp3 = ~etp
                       | tp3;
assign mq_ge_ac = ~(~n_t_77x
                     | ~ad0_low);
assign mq0_gt_ac0 = ~(~bac0
                       | ~mq0_low);
assign etp = ~(~n_t_23x
                | n_t_22x);
// e10: sn7404 
// e11: sn7486 
assign n_t_85x = ~mq11_low
                  ^ mq10_low;
assign n_t_77x = ~mq0_low
                  ^ ~bac0;
assign n_t_34x = n_t_70x
                  ^ mq0_low;
// e12: sn74h11 
assign ac2_mq11_0 = mq_0 & ac2_8_0 & ~ac4_11_0;
assign n_t_64x = etp & shift_ok;
assign bac0 = ac0;
// e13: sn74h74 
always @(ac_load_low, dvi, ad0_low)
  if (~dvi) begin
    n_t_42x_m <= 1'b1;
  end else
  if (~(~ac_load_low)) begin
    n_t_42x_m <= ~ad0_low;
  end
always @(ac_load_low, dvi, n_t_42x_m)
  if (~dvi) begin
    n_t_42x <= 1'b1;
  end else
  if (~ac_load_low) begin
    n_t_42x <= n_t_42x_m;
  end
always @(etp, n_t_73x, init, n_t_74x)
  if (~n_t_73x) begin
    n_t_84x_m <= 1'b0;
  end else
  if (init) begin
    n_t_84x_m <= 1'b1;
  end else
  if (~(etp)) begin
    n_t_84x_m <= n_t_74x;
  end
always @(etp, n_t_73x, init, n_t_84x_m)
  if (~n_t_73x) begin
    n_t_84x <= 1'b0;
  end else
  if (init) begin
    n_t_84x <= 1'b1;
  end else
  if (etp) begin
    n_t_84x <= n_t_84x_m;
  end
// e14: sn7410 
assign n_t_74x = ~dcm_or_dpic_low & last_step_l & shift_ok;
assign n_t_33x = ~(~ac_to_mq_ena_low & ~ts3 & ~ts3);
assign n_t_15x = ~(eae_on & norms_or_shl_or_asr_or_lsr & ~fetch);
// e15: sn7412 
// n_t_4x = !(dvi & carry_out_low & n_t_84x); 
// skip = !(ac2_8_0 & ac_0 & !rom_24_l); 
// e16: dec8235 
// n_t_43x = !(tp3 & !rtf
//        # tp3 & !sam_low); 
// n_t_40x = !(!data1 & !rtf
//        # mq0_gt_ac0 & !sam_low); 
// n_t_40x = !(!'b'1 & !rtf
//        # mq_ge_ac & !sam_low); 
// en2 = !(!'b'1 & !rtf
//    # 'b'1 & !sam_low); 
// e17: sn74h74 
always @(tp2_d, n_t_68x, n_t_67x)
  if (~n_t_68x) begin
    n_t_69x_m <= 1'b0;
  end else
  if (~(~tp2_d)) begin
    n_t_69x_m <= n_t_67x;
  end
always @(tp2_d, n_t_68x, n_t_69x_m)
  if (~n_t_68x) begin
    n_t_69x <= 1'b0;
  end else
  if (~tp2_d) begin
    n_t_69x <= n_t_69x_m;
  end
always @(negedge clock)
  if (~clock) begin
    tp2_d <= n_t_60x;
  end
// e18: sn97401 
// c0 = !(!n_t_19x & modeb); 
// not_last_xfer = !(n_t_69x & n_t_4x); 
// ac_to_bus_low = !(!ts3 & !rom_15_l); 
// carry_in = !(!ts3 & n_t_53x); 
// e19: sn7404 
// e20: dec8235 
// en1 = !(!'b'1 & !n_t_5x
//    # eir3 & !n_t_33x); 
// mq_to_bus_low = !(!n_t_5x
//              # 'b'1 & !n_t_33x); 
// md_disable = !(!eir3 & !n_t_5x); 
// data_t = !(!eir3 & !n_t_5x); 
// e21: sn74h74 
always @(etp_or_tp3, init, n_t_84x)
  if (init) begin
    eae_on_m <= 1'b0;
  end else
  if (~(etp_or_tp3)) begin
    eae_on_m <= ~n_t_84x;
  end
always @(etp_or_tp3, init, eae_on_m)
  if (init) begin
    eae_on <= 1'b0;
  end else
  if (etp_or_tp3) begin
    eae_on <= eae_on_m;
  end
always @(tp2, tp2_d, 1'b1)
  if (tp2_d) begin
    n_t_60x_m <= 1'b0;
  end else
  if (~(~tp2)) begin
    n_t_60x_m <= 1'b1;
  end
always @(tp2, tp2_d, n_t_60x_m)
  if (tp2_d) begin
    n_t_60x <= 1'b0;
  end else
  if (~tp2) begin
    n_t_60x <= n_t_60x_m;
  end
// e22: n8881n 
// link_data = !(!rom_11_l & bac0); 
// link_data = !(!eae_on & dvi); 
// ac_load_low = !(!n_t_33x & tp3); 
// carry_in = !(n_t_56x & next_loc); 
// e23: sn7416 
// link_data = !n_t_49x; 
// ac_to_mq_ena_low = ac_to_mq_ena_low; 
// ac_load_low = !etp; 
// en0 = en2; 
// skip = !next_loc; 
// e24: dec8235 
// ad_lk_low = !(!mq0_low & !lp_shl_or_norms_rp_and_eae_on_low
//          # n_t_34x & !dvi_and_ts3); 
// shl_ena_low = !(shift_ok & !lp_shl_or_norms_rp_and_eae_on_low
//            # 'b'1 & !dvi_and_ts3); 
// mq_data_low = !(!'b'1 & !lp_shl_or_norms_rp_and_eae_on_low
//            # n_t_66x & !dvi_and_ts3); 
// left_low = !(shift_ok & !lp_shl_or_norms_rp_and_eae_on_low); 
// e25: sn97401 
// data_f = !(lp_dcm_or_dpic_or_sam_rp_and_ts3 & eir2); 
// n_t_46x = n_t_33x; 
// en0 = !(n_t_56x & next_loc); 
// carry_in = !(lp_dcm_or_dpic_or_sam_rp_and_ts3 & !eae_on); 
// e26: sn7486 
assign n_t_3x = ~n_t_84x
                 ^ eae_on;
assign n_t_24x = eir3
                  ^ eir2;
assign n_t_92x = n_t_42x
                  ^ n_t_38x;
assign n_t_66x = carry_out_low
                  ^ n_t_92x;
// e27: dec8235 
// en1 = !(mq11_low & !last_dvi_low
//    # 'b'1 & !normal_dvi_low); 
// data_f = !(!mq10_low & !last_dvi_low
//       # n_t_82x & !normal_dvi_low); 
// left_low = !(!'b'1 & !last_dvi_low
//         # div_12_l & !normal_dvi_low); 
// n_t_46x = !(!'b'1 & !last_dvi_low
//        # 'b'1 & !normal_dvi_low); 
// e28: sn7404 
// e29: sp380n 
assign n_t_56x = ~(~msir_disable
                    | ts4);
// e30: sp384n 
assign n_t_52x = ~shift_ok
                  | n_t_46x;
assign dcm_or_dpic_low = ~n_t_24x
                          | rom_22_l;
assign n_t_5x = ts2
                 | ac_to_mq_ena_low;
// e31: dec8235 
// right_low = !(!muy_and_eae_on_low
//          # shift_ok & !lp_asr_or_lsr_rp_and_eae_on_low); 
// en1 = !(!mq11_low & !muy_and_eae_on_low); 
// n_t_43x = !(!'b'1 & !muy_and_eae_on_low
//        # n_t_64x & !lp_asr_or_lsr_rp_and_eae_on_low); 
// n_t_40x = !(!'b'1 & !muy_and_eae_on_low
//        # !mq11_low & !lp_asr_or_lsr_rp_and_eae_on_low); 
// e32: n8881n 
// link_load = !(tp3 & !rom_17_l); 
// link_load = !(n_t_44x & n_t_64x); 
// link_load = !(n_t_64x & n_t_44x); 
// link_load = !(!rom_17_l & tp3); 
// e33: sn7410 
assign last_dvi_low = ~(dvi & ~ts3 & ~last_step_l);
assign n_t_44x = ~last_dvi_low & dcm_or_dpic_low & lp_shl_or_norms_rp_and_eae_on_low;
assign normal_dvi_low = ~(~ts3 & last_step_l & dvi);
// e34: sn7402 
assign norms_or_shl_or_asr_or_lsr = ~(rom_15_l
                                       | ~rom_12_l);
assign dvi = ~rom_14_l
                | rom_12_l;
assign n_t_61x = ~(~eae_on
                    | rom_15_l);
assign n_t_70x = ~(~eae_on
                    | ~mq11_low);
// e35: sn7410 
assign lp_shl_or_norms_rp_and_eae_on_low = ~(~rom_14_l & n_t_61x & rom_12_l);
assign lp_asr_or_lsr_rp_and_eae_on_low = ~rom_12_l & rom_14_l & n_t_61x;
assign muy_and_eae_on_low = ~(~rom_12_l & n_t_61x & rom_14_l);
// e36: n8881n 
// restart = !n_t_3x; 
// restart = !n_t_3x; 
// ac_load_low = !(n_t_4x & tp3); 
// e37: sn97401 
// n_t_46x = !(last_dvi_low & eae_on); 
// n_t_4x = !(dcm_or_dpic_low & rom_15_l); 
// data1 = !(n_t_13x & gtf_or_ind); 
// skip = !(n_t_13x & !sgt_low); 
// e38: sn7400 
assign incr_sc = ~(~rom_15_l & n_t_64x);
assign n_t_67x = ~rom_15_l & dcm_or_dpic_low;
assign dvi_and_ts3 = ~(dvi & ~ts3);
assign sam_low = ~(lp_dcm_or_dpic_or_sam_rp_and_ts3 & ~n_t_24x);
// e39: sn7404 
// e40: sp380n 
assign lp_dcm_or_dpic_or_sam_rp_and_ts3 = ~rom_22_l
                                             | ts3;
assign n_t_68x = ~tp1
                    | n_t_22x;
// e41: sn74h74 
always @(n_t_43x, modeb, n_t_40x)
  if (~modeb) begin
    n_t_13x_m <= 1'b0;
  end else
  if (~(~n_t_43x)) begin
    n_t_13x_m <= ~n_t_40x;
  end
always @(n_t_43x, modeb, n_t_13x_m)
  if (~modeb) begin
    n_t_13x <= 1'b0;
  end else
  if (~n_t_43x) begin
    n_t_13x <= n_t_13x_m;
  end
// e42: sn7404 
// e43: dm8093 
assign mq_load = ~n_t_52x? etp_or_tp3: 1'bz;
// r1: r_us_ 
// r2: r_us_ 
// r3: r_us_ 
// r4: r_us_ 
// r5: r_us_ 
// r6: r_us_ 
// r7: r_us_ 
// r8: r_us_ 
// r9: r_us_ 
// r10: r_us_ 
// r11: r_us_ 
// r12: r_us_ 
// r13: r_us_ 
// r14: r_us_ 
// r15: r_us_ 
// r16: r_us_ 
// r17: r_us_ 
// r18: r_us_ 
// r19: r_us_ 
// r20: r_us_ 
// Open collector 'wire-or's 
assign ac_load_low = (~n_t_33x & tp3)
                      | etp
                      | n_t_4x & tp3? 1'b0: 1'bz;
assign ac_to_bus_low = (~ts3 & ~rom_15_l)? 1'b0: 1'bz;
assign ac_to_mq_ena_low = ~(dad_or_dst_low
                           | e)? dad_or_dst_low
                           | e: 1'bz;
assign ad_lk_low = (~mq0_low & ~lp_shl_or_norms_rp_and_eae_on_low
                     | n_t_34x & ~dvi_and_ts3)? 1'b0: 1'bz;
assign c0 = (~n_t_19x & modeb)? 1'b0: 1'bz;
assign carry_in = (~ts3 & n_t_53x)
                   | n_t_56x & next_loc
                   | (lp_dcm_or_dpic_or_sam_rp_and_ts3 & ~eae_on)? 1'b0: 1'bz;
assign data1 = n_t_13x & gtf_or_ind? ~n_t_13x & gtf_or_ind: 1'bz;
assign data_f = lp_dcm_or_dpic_or_sam_rp_and_ts3 & eir2
                 | (~mq10_low & ~last_dvi_low
                    | n_t_82x & ~normal_dvi_low)? 1'b0: 1'bz;
assign data_t = (~eir3 & ~n_t_5x)? 1'b0: 1'bz;
assign en0 = (~en2)
              | n_t_56x & next_loc? 1'b0: 1'bz;
assign en1 = (eir3 & ~n_t_33x)
              | (mq11_low & ~last_dvi_low
                 | ~normal_dvi_low)
              | (~mq11_low & ~muy_and_eae_on_low)? 1'b0: 1'bz;
assign en2 = (~sam_low)? 1'b0: 1'bz;
assign shift_ok = ~((ac0_ne_ac1 & n_t_18x
                      | modeb & ~last_step_l & norms_or_shl_or_asr_or_lsr
                      | ac2_mq11_0 & ~n_t_28x));
assign left_low = (shift_ok & ~lp_shl_or_norms_rp_and_eae_on_low)
                   | (div_12_l & ~normal_dvi_low)? 1'b0: 1'bz;
assign link_data = (~rom_11_l & bac0)
                    | (~eae_on & dvi)
                    | n_t_49x? 1'b0: 1'bz;
assign link_load = (tp3 & ~rom_17_l)
                    | n_t_44x & n_t_64x
                    | n_t_64x & n_t_44x
                    | (~rom_17_l & tp3)? 1'b0: 1'bz;
assign md_disable = (~eir3 & ~n_t_5x)? 1'b0: 1'bz;
assign mq_data_low = (n_t_66x & ~dvi_and_ts3)? 1'b0: 1'bz;
assign mq_to_bus_low = (~n_t_5x
                         | ~n_t_33x)? 1'b0: 1'bz;
assign n_t_40x = ~((~data1 & ~rtf
                     | mq0_gt_ac0 & ~sam_low)
                    | (mq_ge_ac & ~sam_low)
                    | (~mq11_low & ~lp_asr_or_lsr_rp_and_eae_on_low));
assign n_t_43x = ~((tp3 & ~rtf
                     | tp3 & ~sam_low)
                    | (n_t_64x & ~lp_asr_or_lsr_rp_and_eae_on_low));
assign n_t_46x = ~((~n_t_33x)
                    | (~normal_dvi_low)
                    | last_dvi_low & eae_on);
assign n_t_4x = ~dvi & carry_out_low & n_t_84x
                   | dcm_or_dpic_low & rom_15_l;
assign not_last_xfer = n_t_69x & n_t_4x? ~n_t_69x & n_t_4x: 1'bz;
assign restart = n_t_3x? ~n_t_3x: 1'bz;
assign right_low = (~muy_and_eae_on_low
                     | shift_ok & ~lp_asr_or_lsr_rp_and_eae_on_low)? 1'b0: 1'bz;
assign shl_ena_low = (shift_ok & ~lp_shl_or_norms_rp_and_eae_on_low
                       | ~dvi_and_ts3)? 1'b0: 1'bz;
assign skip = (ac2_8_0 & ac_0 & ~rom_24_l)
               | next_loc
               | (n_t_13x & ~sgt_low)? 1'b0: 1'bz;
endmodule