// this file is generated by topld.pl 
// please don't edit it. 
// input pins 
// output pins 
module m8650 (/*n_t_103x,*/
tp_ca1, 
serial_in, sw1, sw2, sw3, 
//sw4, sw5, sw6, 
c0_l, c1_l, clk, data04_l, data05_l, data06_l, data07_l, data08_l, data09_l, data10_l, data11_l, initialize, /*int_enab,*/ int_rqst_l, internal_io_l, io_pause_l, md03_l, md04_l, md05_l, md06_l, md07_l, md08_l, md09_l, md10_l, md11_l, power_ok, /*r_run_l,*/ serial_out, skip_l, 
tp_ab1, tp_ba1, tp_bb1, 
tp3/*, tx_div_l*/);
// VRS Kludge
output tp_ca1;
//input n_t_103x; //VRS
input serial_in;
input sw1;
input sw2;
input sw3;
//input sw4;
//input sw5;
//input sw6;
output tp_ab1, tp_ba1, tp_bb1;
output c0_l;
output c1_l;
input clk;
inout data04_l;
inout data05_l;
inout data06_l;
inout data07_l;
inout data08_l;
inout data09_l;
inout data10_l;
inout data11_l;
input initialize;
//inout int_enab; //VRS
output int_rqst_l;
output internal_io_l;
input io_pause_l;
input md03_l;
input md04_l;
input md05_l;
input md06_l;
input md07_l;
input md08_l;
input md09_l;
input md10_l;
input md11_l;
input power_ok;
//output reg r_run_l; //VRS
output reg serial_out;
inout skip_l;
input tp3;
//inout tx_div_l; //VRS

reg r_run_l;

reg bd1745_m;
reg ck_pulse_m;
reg enab_m;
reg gdollar_0_m;
reg gdollar_4_m;
reg gdollar_5_m;
reg int_enab_l_m;
reg last_unit_m;
reg n_t_2x_m;
reg n_t_56x_m;
reg n_t_5x_m;
reg n_t_60x_m;
reg n_t_61x_m;
reg n_t_62x_m;
reg n_t_63x_m;
reg n_t_65x_m;
reg n_t_66x_m;
reg p_pulse_l_m;
reg r_run_l_m;
reg rflg_l_m;
reg rx_active_m;
reg rx_div2_l_m;
reg rx_div4_l_m;
reg rx_div8_m;
reg serial_out_m;
reg spike_det_l_m;
reg start_l_m;
reg stp1_m;
reg stp2_m;
reg tflg_l_m;
reg tx_active_l_m;
reg tx_data_m;
reg tx_div_m;

reg rx_div;
reg ck_pulse;
reg rx_div2_l;
reg rx_div4_l;
reg n_t_2x;
reg n_t_5x;
reg gdollar_0;
reg bd1745;
reg rx7;
reg n_t_34x;
reg n_t_36x;
reg n_t_35x;
reg rx_active;
reg p_pulse_l;
reg last_unit;
reg rx_div8;
reg bd1200;
reg bd600;
reg bd300;
reg bd150;
reg n_t_37x;
reg n_t_38x;
reg n_t_39x;
reg n_t_40x;
reg bd873;
reg bd436;
reg bd218;
reg bd109;
reg bd19200;
reg bd9600;
reg bd4800;
reg bd2400;
reg tx_div;
reg spike_det_l;
reg bd614400;
reg bd307200;
reg bd153600;
reg bd76800;
reg bd38400;
reg gdollar_1;
reg gdollar_2;
reg gdollar_3;
reg tx_active_l;
reg start_l;
reg stp1;
reg gdollar_4;
reg stp2;
reg gdollar_5;
reg n_t_60x;
reg n_t_62x;
reg n_t_56x;
reg n_t_61x;
reg enab;
reg n_t_63x;
reg n_t_65x;
reg n_t_66x;
reg tx_data;
reg tflg_l;
reg int_enab_l;
reg rflg_l;
// internal nodes 
wire ckkcc_l;
wire ckkcf;
wire ckkie;
wire cktcf;
wire cktfl;
wire div11;
wire dokcc;
wire dokrs;
wire dotcf;
wire dotpc;
wire flgs;
wire iot03_l;
wire iot04_l;
wire iot0x_l;
wire iot11_l;
wire iot12_l;
wire iot1x_l;
wire iot34_l;
wire iot35_l;
wire iot3x_l;
wire iot40_l;
wire iot41_l;
wire iot42_l;
wire iot43_l;
wire iot44_l;
wire iot45_l;
wire iot46_l;
wire iot47_l;
wire iot4x_l;
wire is110;
wire kcc_l;
wire kcf_l;
wire kie_l;
wire krb_l;
wire krs_l;
wire ksf_l;
wire kskp;
wire n_t_108x;
wire n_t_11x;
wire n_t_16x;
wire n_t_19x;
wire n_t_21x;
wire n_t_23x;
wire n_t_25x;
wire n_t_28x;
wire n_t_29x;
wire n_t_41x;
wire n_t_42x;
wire n_t_46x;
wire n_t_47x;
wire n_t_48x;
wire n_t_49x;
wire n_t_52x;
wire n_t_53x;
wire n_t_54x;
wire n_t_55x;
wire n_t_68x;
wire n_t_69x;
wire n_t_70x;
wire n_t_76x;
wire n_t_81x;
wire n_t_8x;
wire n_t_91x;
wire n_t_94x;
wire n_t_9x;
wire rx_active8_l;
wire rx_again_l;
wire rx_bot;
wire rx_last_l;
wire rx_rate;
wire rx_sel;
wire selected_l;
wire stp_mark;
wire tcf_l;
wire tfl_l;
wire tkskp;
wire tls_l;
wire tpc_l;
wire tsf_l;
wire tsk_l;
wire tskp;
wire tx7;
wire tx8;
wire tx_sel;
wire tx_shift_l;
// code nodes 

// VRS Kludges
// n$103 is supposed to be a delayed tx_div_l.
assign n_t_103x = ~tx_active_l;
//assign n_t_103x = 1'b1;
// Stub out switches that map to the test points.
assign sw4 = 1'b1; // Set device code to 12.
assign sw5 = 1'b1;
assign sw6 = 1'b1;
// Output debug information on CA1.
//assign tp_ca1 = tx_active_l;
assign tp_ca1 = tp3;
assign tp_bb1 = dotpc;
assign tp_ba1 = tx_div;
assign tp_ab1 = tx_shift_l;

// equations 
// c1: c_us 
// c2: c_us 
// c3: c_us 
// c4: c_us 
// c5: c_us 
// c6: c_us 
// c7: c_us 
// c8: c_us 
// c9: c_us 
// c10: c_us 
// c11: c_us 
// c12: c_us 
// c13: c_us 
// c14: c_us 
// c15: c_us 
// c16: c_us 
// c17: c_us 
// c18: c_us 
// c19: c_us 
// c20: c_us 
// c21: c_us 
// c22: c_us 
// c23: c_us 
// c24: c_us 
// c25: c_us 
// c26: c_us 
// c27: c_us 
// c28: c_us 
// c29: c_us 
// c30: c_us 
// c31: c_us 
// c33: c_us 
// c34: c_us 
// c35: c_us 
// c36: c_us 
// c37: c_us 
// c38: c_us 
// c39: c_us 
// c40: c_us 
// c41: c_us 
// c42: c_us 
// c43: c_us 
// c44: c_us 
// c45: c_us 
// c46: c_us 
// c47: c_us 
// c48: c_us 
// c49: c_us 
// c50: c_us 
// c51: cpol_use 
// c52: cpol_use 
// c53: cpol_use 
// c56: cpol_use 
// c57: c_us 
// e1: sp380n 
// e2: sn97401 
// data07_l = !(n_t_35x & dokrs); 
// data06_l = !(dokrs & n_t_36x); 
// data05_l = !(n_t_34x & dokrs); 
// data04_l = !(dokrs & rx7); 
// e3: sn7474 
always @(posedge rx_rate)
  if (rx_rate) begin
    rx_div <= n_t_76x;
  end
always @(rx_active8_l, rx_rate, 1'b1)
  if (~rx_rate) begin
    ck_pulse_m <= 1'b0;
  end else
  if (~(~rx_active8_l)) begin
    ck_pulse_m <= 1'b1;
  end
always @(rx_active8_l, rx_rate, ck_pulse_m)
  if (~rx_rate) begin
    ck_pulse <= 1'b0;
  end else
  if (~rx_active8_l) begin
    ck_pulse <= ck_pulse_m;
  end
// e4: sn7474 
always @(rx_div, rx_last_l, rx_div2_l)
  if (~rx_last_l) begin
    rx_div2_l_m <= 1'b1;
  end else
  if (~(~rx_div)) begin
    rx_div2_l_m <= ~rx_div2_l;
  end
always @(rx_div, rx_last_l, rx_div2_l_m)
  if (~rx_last_l) begin
    rx_div2_l <= 1'b1;
  end else
  if (~rx_div) begin
    rx_div2_l <= rx_div2_l_m;
  end
always @(rx_div2_l, rx_last_l, rx_div4_l)
  if (~rx_last_l) begin
    rx_div4_l_m <= 1'b1;
  end else
  if (~(rx_div2_l)) begin
    rx_div4_l_m <= ~rx_div4_l;
  end
always @(rx_div2_l, rx_last_l, rx_div4_l_m)
  if (~rx_last_l) begin
    rx_div4_l <= 1'b1;
  end else
  if (rx_div2_l) begin
    rx_div4_l <= rx_div4_l_m;
  end
// e5: sn7493
/*
reg [3:0] ctr110;
always @(posedge bd19200) begin
  if (ctr110 == 10) begin
    ctr110 <= 0;
	 bd1745 <= 1;
  end else begin
    ctr110 <= ctr110 + 1;
	 bd1745 <= 0;
  end
end
*/
always @(bd19200, div11, n_t_2x)
  if (div11) begin
    n_t_2x_m <= 1'b0;
  end else
  if ((bd19200)) begin
    n_t_2x_m <= ~n_t_2x;
  end
always @(bd19200, div11, n_t_2x_m)
  if (div11) begin
    n_t_2x <= 1'b0;
  end else
  if (~bd19200) begin
    n_t_2x <= n_t_2x_m;
  end
always @(n_t_2x, div11, n_t_5x)
  if (div11) begin
    n_t_5x_m <= 1'b0;
  end else
  if ((n_t_2x)) begin
    n_t_5x_m <= ~n_t_5x;
  end
always @(n_t_2x, div11, n_t_5x_m)
  if (div11) begin
    n_t_5x <= 1'b0;
  end else
  if (~n_t_2x) begin
    n_t_5x <= n_t_5x_m;
  end
always @(n_t_5x, div11, gdollar_0)
  if (div11) begin
    gdollar_0_m <= 1'b0;
  end else
  if ((n_t_5x)) begin
    gdollar_0_m <= ~gdollar_0;
  end
always @(n_t_5x, div11, gdollar_0_m)
  if (div11) begin
    gdollar_0 <= 1'b0;
  end else
  if (~n_t_5x) begin
    gdollar_0 <= gdollar_0_m;
  end
always @(gdollar_0, div11, bd1745)
  if (div11) begin
    bd1745_m <= 1'b0;
  end else
  if ((gdollar_0)) begin
    bd1745_m <= ~bd1745;
  end
always @(gdollar_0, div11, bd1745_m)
  if (div11) begin
    bd1745 <= 1'b0;
  end else
  if (~gdollar_0) begin
    bd1745 <= bd1745_m;
  end
// e6: dec8271 
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    rx7 <= ~serial_in & p_pulse_l
                | ~p_pulse_l;
  end
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    n_t_34x <= rx7 & p_pulse_l
                    | ~p_pulse_l;
  end
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    n_t_36x <= n_t_34x & p_pulse_l
                    | ~p_pulse_l;
  end
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    n_t_35x <= n_t_36x & p_pulse_l
                    | ~p_pulse_l;
  end
// e7: sn7474 
always @(n_t_70x, power_ok, rx_again_l, 1'b0)
  if (~power_ok) begin
    rx_active_m <= 1'b0;
  end else
  if (~rx_again_l) begin
    rx_active_m <= 1'b1;
  end else
  if (~(~n_t_70x)) begin
    rx_active_m <= 1'b0;
  end
always @(n_t_70x, power_ok, rx_again_l, rx_active_m)
  if (~power_ok) begin
    rx_active <= 1'b0;
  end else
  if (~rx_again_l) begin
    rx_active <= 1'b1;
  end else
  if (~n_t_70x) begin
    rx_active <= rx_active_m;
  end
always @(rx_active, rx_div4_l, 1'b0)
  if (~rx_div4_l) begin
    p_pulse_l_m <= 1'b1;
  end else
  if (~(rx_active)) begin
    p_pulse_l_m <= 1'b0;
  end
always @(rx_active, rx_div4_l, p_pulse_l_m)
  if (~rx_div4_l) begin
    p_pulse_l <= 1'b1;
  end else
  if (rx_active) begin
    p_pulse_l <= p_pulse_l_m;
  end
// e8: sn7474 
always @(ck_pulse, n_t_91x, rx_bot)
  if (~n_t_91x) begin
    last_unit_m <= 1'b0;
  end else
  if (~(ck_pulse)) begin
    last_unit_m <= rx_bot;
  end
always @(ck_pulse, n_t_91x, last_unit_m)
  if (~n_t_91x) begin
    last_unit <= 1'b0;
  end else
  if (ck_pulse) begin
    last_unit <= last_unit_m;
  end
always @(rx_div4_l, rx_last_l, rx_div8)
  if (~rx_last_l) begin
    rx_div8_m <= 1'b0;
  end else
  if (~(rx_div4_l)) begin
    rx_div8_m <= ~rx_div8;
  end
always @(rx_div4_l, rx_last_l, rx_div8_m)
  if (~rx_last_l) begin
    rx_div8 <= 1'b0;
  end else
  if (rx_div4_l) begin
    rx_div8 <= rx_div8_m;
  end
// e9: sn7493 
always @(posedge bd2400)
  if (bd2400) begin
    bd1200 <= ~bd1200;
  end
always @(posedge bd1200)
  if (bd1200) begin
    bd600 <= ~bd600;
  end
always @(posedge bd600)
  if (bd600) begin
    bd300 <= ~bd300;
  end
always @(posedge bd300)
  if (bd300) begin
    bd150 <= ~bd150;
  end
// e10: dec8271 
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    n_t_37x <= n_t_35x & p_pulse_l
                    | ~p_pulse_l;
  end
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    n_t_38x <= n_t_37x & p_pulse_l
                    | ~p_pulse_l;
  end
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    n_t_39x <= n_t_38x & p_pulse_l
                    | ~p_pulse_l;
  end
always @(negedge n_t_41x)
  if (~n_t_41x) begin
    n_t_40x <= n_t_39x & p_pulse_l
                    | ~p_pulse_l;
  end
assign rx_bot = ~n_t_40x;
// e11: sn7402 
assign n_t_81x = ~(spike_det_l
                    | serial_in);
assign n_t_41x = ~(ck_pulse
                    | n_t_42x);
assign n_t_42x = ~(p_pulse_l
                    | rx_div2_l);
// e12: sn7400 
assign rx_active8_l = ~(rx_active & rx_div8);
assign n_t_91x = ~(~rx_active & rx_div8);
assign n_t_76x = ~(rx_div & rx_last_l);
assign rx_last_l = ~(~last_unit & ~rx_active);
// e13: sn7493 
always @(posedge bd1745)
  if (bd1745) begin
    bd873 <= ~bd873;
  end
always @(posedge bd873)
  if (bd873) begin
    bd436 <= ~bd436;
  end
always @(posedge bd436)
  if (bd436) begin
    bd218 <= ~bd218;
  end
always @(posedge bd218)
  if (bd218) begin
    bd109 <= ~bd109;
  end
// e14: sn7493 
always @(posedge bd38400)
  if (bd38400) begin
    bd19200 <= ~bd19200;
  end
always @(posedge bd19200)
  if (bd19200) begin
    bd9600 <= ~bd9600;
  end
always @(posedge bd9600)
  if (bd9600) begin
    bd4800 <= ~bd4800;
  end
always @(posedge bd4800)
  if (bd4800) begin
    bd2400 <= ~bd2400;
  end
// e15: sn97401 
// data11_l = !(n_t_40x & dokrs); 
// data10_l = !(dokrs & n_t_39x); 
// data09_l = !(n_t_38x & dokrs); 
// data08_l = !(dokrs & n_t_37x); 
// e16: sn7474 
always @(rx_rate, initialize, n_t_94x)
  if (initialize) begin
    tx_div_m <= 1'b1;
  end else
  if (~(rx_rate)) begin
    tx_div_m <= n_t_94x;
  end
always @(rx_rate, initialize, tx_div_m)
  if (initialize) begin
    tx_div <= 1'b1;
  end else
  if (rx_rate) begin
    tx_div <= tx_div_m;
  end
assign tx_div_l = ~tx_div;
always @(rx_active8_l, rx_again_l, initialize, 1'b1)
  if (~rx_again_l) begin
    spike_det_l_m <= 1'b0;
  end else
  if (initialize) begin
    spike_det_l_m <= 1'b1;
  end else
  if (~(rx_active8_l)) begin
    spike_det_l_m <= 1'b1;
  end
always @(rx_active8_l, rx_again_l, initialize, spike_det_l_m)
  if (~rx_again_l) begin
    spike_det_l <= 1'b0;
  end else
  if (initialize) begin
    spike_det_l <= 1'b1;
  end else
  if (rx_active8_l) begin
    spike_det_l <= spike_det_l_m;
  end
// e17: sn7493 
always @(posedge clk)
  if (clk) begin
    bd614400 <= ~bd614400;
  end
always @(posedge bd614400)
  if (bd614400) begin
    bd307200 <= ~bd307200;
  end
always @(posedge bd307200)
  if (bd307200) begin
    bd153600 <= ~bd153600;
  end
always @(posedge bd153600)
  if (bd153600) begin
    bd76800 <= ~bd76800;
  end
// e18: sn7493 
always @(posedge bd76800)
  if (bd76800) begin
    bd38400 <= ~bd38400;
  end
always @(posedge 1'b0)
  if (1'b0) begin
    gdollar_1 <= ~gdollar_1;
  end
always @(posedge gdollar_1)
  if (gdollar_1) begin
    gdollar_2 <= ~gdollar_2;
  end
always @(posedge gdollar_2)
  if (gdollar_2) begin
    gdollar_3 <= ~gdollar_3;
  end
// e19: sn7410 
assign rx_again_l = ~(serial_in & ~rx_last_l & rx_rate);
assign tx8 = ~(n_t_68x & tx_div_l & n_t_69x);
assign tx7 = ~(n_t_69x & n_t_68x);
// e20: sn7474 
always @(rx_rate, initialize, n_t_108x)
  if (initialize) begin
    tx_active_l_m <= 1'b1;
  end else
  if (~(rx_rate)) begin
    tx_active_l_m <= n_t_108x;
  end
always @(rx_rate, initialize, tx_active_l_m)
  if (initialize) begin
    tx_active_l <= 1'b1;
  end else
  if (rx_rate) begin
    tx_active_l <= tx_active_l_m;
  end
always @(tx_active_l, rx_rate, 1'b0)
  if (~rx_rate) begin
    start_l_m <= 1'b1;
  end else
  if (~(~tx_active_l)) begin
    start_l_m <= 1'b0;
  end
always @(tx_active_l, rx_rate, start_l_m)
  if (~rx_rate) begin
    start_l <= 1'b1;
  end else
  if (~tx_active_l) begin
    start_l <= start_l_m;
  end
// e21: sn7404 
// e23: sp380n 
assign selected_l = ~(rx_sel
                       | tx_sel);
assign n_t_11x = ~(stp1
                    | is110);
assign n_t_9x = ~(~is110
                   | stp2);
assign stp_mark = ~(n_t_11x
                     | n_t_9x);
// e24: n8815 
assign n_t_69x = ~(n_t_56x
                    | enab
                    | n_t_60x
                    | n_t_62x);
assign n_t_68x = ~(n_t_63x
                    | n_t_65x
                    | n_t_66x
                    | n_t_61x);
// e25: sn7450 
assign n_t_108x = ~(stp_mark & enab
                     | ~tx_active_l & tx8);
assign tx_shift_l = ~(tp3 & dotpc
                       | tx_div & n_t_103x);
// e26: dec8271 
always @(rx_rate, tx_div, tx_active_l)
  if (~tx_div) begin
    stp1_m <= 1'b0;
  end else
  if (~(rx_rate)) begin
    stp1_m <= tx_active_l;
  end
always @(rx_rate, tx_div, stp1_m)
  if (~tx_div) begin
    stp1 <= 1'b0;
  end else
  if (rx_rate) begin
    stp1 <= stp1_m;
  end
always @(rx_rate, tx_div, stp1)
  if (~tx_div) begin
    gdollar_4_m <= 1'b0;
  end else
  if (~(rx_rate)) begin
    gdollar_4_m <= stp1;
  end
always @(rx_rate, tx_div, gdollar_4_m)
  if (~tx_div) begin
    gdollar_4 <= 1'b0;
  end else
  if (rx_rate) begin
    gdollar_4 <= gdollar_4_m;
  end
always @(rx_rate, tx_div, gdollar_4)
  if (~tx_div) begin
    stp2_m <= 1'b0;
  end else
  if (~(rx_rate)) begin
    stp2_m <= gdollar_4;
  end
always @(rx_rate, tx_div, stp2_m)
  if (~tx_div) begin
    stp2 <= 1'b0;
  end else
  if (rx_rate) begin
    stp2 <= stp2_m;
  end
always @(rx_rate, tx_div, stp2)
  if (~tx_div) begin
    gdollar_5_m <= 1'b0;
  end else
  if (~(rx_rate)) begin
    gdollar_5_m <= stp2;
  end
always @(rx_rate, tx_div, gdollar_5_m)
  if (~tx_div) begin
    gdollar_5 <= 1'b0;
  end else
  if (rx_rate) begin
    gdollar_5 <= gdollar_5_m;
  end
// e27: sp380n 
assign n_t_47x = ~(data05_l
                    | ~dotpc);
assign n_t_46x = ~(~dotpc
                    | data04_l);
assign n_t_49x = ~(data07_l
                    | ~dotpc);
assign n_t_48x = ~(~dotpc
                    | data06_l);
// e28: dec8271 
always @(tx_shift_l, initialize, enab, dotpc, n_t_46x, dotpc)
  if (initialize) begin
    n_t_60x_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    n_t_60x_m <= enab & ~dotpc
                    | n_t_46x & dotpc;
  end
always @(tx_shift_l, initialize, n_t_60x_m)
  if (initialize) begin
    n_t_60x <= 1'b0;
  end else
  if (~tx_shift_l) begin
    n_t_60x <= n_t_60x_m;
  end
always @(tx_shift_l, initialize, n_t_60x, dotpc, n_t_47x, dotpc)
  if (initialize) begin
    n_t_62x_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    n_t_62x_m <= n_t_60x & ~dotpc
                    | n_t_47x & dotpc;
  end
always @(tx_shift_l, initialize, n_t_62x_m)
  if (initialize) begin
    n_t_62x <= 1'b0;
  end else
  if (~tx_shift_l) begin
    n_t_62x <= n_t_62x_m;
  end
always @(tx_shift_l, initialize, n_t_62x, dotpc, n_t_48x, dotpc)
  if (initialize) begin
    n_t_56x_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    n_t_56x_m <= n_t_62x & ~dotpc
                    | n_t_48x & dotpc;
  end
always @(tx_shift_l, initialize, n_t_56x_m)
  if (initialize) begin
    n_t_56x <= 1'b0;
  end else
  if (~tx_shift_l) begin
    n_t_56x <= n_t_56x_m;
  end
always @(tx_shift_l, initialize, n_t_56x, dotpc, n_t_49x, dotpc)
  if (initialize) begin
    n_t_61x_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    n_t_61x_m <= n_t_56x & ~dotpc
                    | n_t_49x & dotpc;
  end
always @(tx_shift_l, initialize, n_t_61x_m)
  if (initialize) begin
    n_t_61x <= 1'b0;
  end else
  if (~tx_shift_l) begin
    n_t_61x <= n_t_61x_m;
  end
// e29: sn7474 
always @(tx_div, tx_active_l, start_l, tx_data)
  if (tx_active_l) begin
    serial_out_m <= 1'b0;
  end else
  if (~start_l) begin
    serial_out_m <= 1'b1;
  end else
  if (~(tx_div)) begin
    serial_out_m <= ~tx_data;
  end
always @(tx_div, tx_active_l, start_l, serial_out_m)
  if (tx_active_l) begin
    serial_out <= 1'b0;
  end else
  if (~start_l) begin
    serial_out <= 1'b1;
  end else
  if (tx_div) begin
    serial_out <= serial_out_m;
  end
always @(tx_shift_l, initialize, dotpc)
  if (initialize) begin
    enab_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    enab_m <= dotpc;
  end
always @(tx_shift_l, initialize, enab_m)
  if (initialize) begin
    enab <= 1'b0;
  end else
  if (~tx_shift_l) begin
    enab <= enab_m;
  end
// e30: sp380n 
assign n_t_53x = ~(data09_l
                    | ~dotpc);
assign n_t_52x = ~(~dotpc
                    | data08_l);
assign n_t_55x = ~(data11_l
                    | ~dotpc);
assign n_t_54x = ~(~dotpc
                    | data10_l);
// e31: dec8271 
always @(tx_shift_l, initialize, n_t_61x, dotpc, n_t_52x, dotpc)
  if (initialize) begin
    n_t_63x_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    n_t_63x_m <= n_t_61x & ~dotpc
                    | n_t_52x & dotpc;
  end
always @(tx_shift_l, initialize, n_t_63x_m)
  if (initialize) begin
    n_t_63x <= 1'b0;
  end else
  if (~tx_shift_l) begin
    n_t_63x <= n_t_63x_m;
  end
always @(tx_shift_l, initialize, n_t_63x, dotpc, n_t_53x, dotpc)
  if (initialize) begin
    n_t_65x_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    n_t_65x_m <= n_t_63x & ~dotpc
                    | n_t_53x & dotpc;
  end
always @(tx_shift_l, initialize, n_t_65x_m)
  if (initialize) begin
    n_t_65x <= 1'b0;
  end else
  if (~tx_shift_l) begin
    n_t_65x <= n_t_65x_m;
  end
always @(tx_shift_l, initialize, n_t_65x, dotpc, n_t_54x, dotpc)
  if (initialize) begin
    n_t_66x_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    n_t_66x_m <= n_t_65x & ~dotpc
                    | n_t_54x & dotpc;
  end
always @(tx_shift_l, initialize, n_t_66x_m)
  if (initialize) begin
    n_t_66x <= 1'b0;
  end else
  if (~tx_shift_l) begin
    n_t_66x <= n_t_66x_m;
  end
always @(tx_shift_l, initialize, n_t_66x, dotpc, n_t_55x, dotpc)
  if (initialize) begin
    tx_data_m <= 1'b0;
  end else
  if (~(~tx_shift_l)) begin
    tx_data_m <= n_t_66x & ~dotpc
                    | n_t_55x & dotpc;
  end
always @(tx_shift_l, initialize, tx_data_m)
  if (initialize) begin
    tx_data <= 1'b0;
  end else
  if (~tx_shift_l) begin
    tx_data <= tx_data_m;
  end
// e33: sn97401 
// c0_l = !dokcc; 
// c1_l = !dokrs; 
// !tx_sel = !tx_sel; 
// c1_l = !dokcc; 
// e34: sp384n 
assign n_t_8x = io_pause_l
                 | data11_l;
// e35: sn74h00 
assign n_t_29x = ~(ckkcc_l & ~initialize);
assign n_t_94x = ~(tx_div & ~tx_active_l);
// e36: sp384n 
// e37: sn97401 
// internal_io_l = !tx_sel; 
// internal_io_l = !rx_sel; 
// skip_l = skip_l; 
// int_rqst_l = !(flgs & int_enab); 
// e38: sn7474 
always @(tx_div, cktfl, n_t_16x, tx7)
  if (cktfl) begin
    tflg_l_m <= 1'b0;
  end else
  if (n_t_16x) begin
    tflg_l_m <= 1'b1;
  end else
  if (~(tx_div)) begin
    tflg_l_m <= tx7;
  end
always @(tx_div, cktfl, n_t_16x, tflg_l_m)
  if (cktfl) begin
    tflg_l <= 1'b0;
  end else
  if (n_t_16x) begin
    tflg_l <= 1'b1;
  end else
  if (tx_div) begin
    tflg_l <= tflg_l_m;
  end
always @(ckkie, initialize, n_t_8x)
  if (initialize) begin
    int_enab_l_m <= 1'b0;
  end else
  if (~(ckkie)) begin
    int_enab_l_m <= n_t_8x;
  end
always @(ckkie, initialize, int_enab_l_m)
  if (initialize) begin
    int_enab_l <= 1'b0;
  end else
  if (ckkie) begin
    int_enab_l <= int_enab_l_m;
  end
assign int_enab = ~int_enab_l;
// e39: sn7450 
assign n_t_70x = ~(rx_active8_l & last_unit
                    | n_t_81x & ck_pulse);
// e40: dec8251 
assign tfl_l = ~(tx_sel & ~n_t_23x & ~n_t_21x & ~n_t_25x);
assign tsf_l = ~(tx_sel & ~n_t_23x & ~n_t_21x & n_t_25x);
assign tcf_l = ~(tx_sel & ~n_t_23x & n_t_21x & ~n_t_25x);
assign tpc_l = ~(tx_sel & n_t_23x & ~n_t_21x & ~n_t_25x);
assign tsk_l = ~(tx_sel & n_t_23x & ~n_t_21x & n_t_25x);
assign tls_l = ~(tx_sel & n_t_23x & n_t_21x & ~n_t_25x);
// e41: sn7400 
assign n_t_16x = ~(~initialize & cktcf);
assign dotpc = ~(tls_l & tpc_l);
assign dotcf = ~(tls_l & tcf_l);
assign cktcf = ~(dotcf & tp3);
// e42: sn7404 
// e43: dec8251 
assign kcf_l = ~(rx_sel & ~n_t_23x & ~n_t_21x & ~n_t_25x);
assign ksf_l = ~(rx_sel & ~n_t_23x & ~n_t_21x & n_t_25x);
assign kcc_l = ~(rx_sel & ~n_t_23x & n_t_21x & ~n_t_25x);
assign krs_l = ~(rx_sel & n_t_23x & ~n_t_21x & ~n_t_25x);
assign kie_l = ~(rx_sel & n_t_23x & ~n_t_21x & n_t_25x);
assign krb_l = ~(rx_sel & n_t_23x & n_t_21x & ~n_t_25x);
// e44: sn7400 
assign flgs = ~(rflg_l & tflg_l);
assign dokrs = ~(krb_l & krs_l);
assign dokcc = ~(krb_l & kcc_l);
assign ckkcc_l = ~(dokcc & tp3);
// e45: sn7402 
assign cktfl = ~(tfl_l
                  | ~tp3);
assign tkskp = ~(~(kskp
                    | tskp));
assign n_t_19x = ~(tsk_l
                    | int_enab_l);
assign tskp = ~(tflg_l
                 | tsf_l);
// e46: sp380n 
assign n_t_21x = ~(md10_l
                    | selected_l);
assign n_t_23x = ~(selected_l
                    | md09_l);
assign n_t_25x = ~(md11_l
                    | selected_l);
// e47: sn7402 
assign n_t_28x = ~(n_t_29x
                    | ckkcf);
assign ckkcf = ~(~tp3
                  | kcf_l);
assign ckkie = ~(kie_l
                  | ~tp3);
assign kskp = ~(ksf_l
                 | rflg_l);
// e48: sn7474 
always @(ck_pulse, n_t_28x, rx_bot)
  if (~n_t_28x) begin
    rflg_l_m <= 1'b1;
  end else
  if (~(ck_pulse)) begin
    rflg_l_m <= ~rx_bot;
  end
always @(ck_pulse, n_t_28x, rflg_l_m)
  if (~n_t_28x) begin
    rflg_l <= 1'b1;
  end else
  if (ck_pulse) begin
    rflg_l <= rflg_l_m;
  end
always @(rx7, ckkcc_l, initialize, 1'b1)
  if (~ckkcc_l) begin
    r_run_l_m <= 1'b0;
  end else
  if (initialize) begin
    r_run_l_m <= 1'b1;
  end else
  if (~(~rx7)) begin
    r_run_l_m <= 1'b1;
  end
always @(rx7, ckkcc_l, initialize, r_run_l_m)
  if (~ckkcc_l) begin
    r_run_l <= 1'b0;
  end else
  if (initialize) begin
    r_run_l <= 1'b1;
  end else
  if (~rx7) begin
    r_run_l <= r_run_l_m;
  end
// ic1: sn74138 
assign iot4x_l = ~(~md03_l & md04_l & md05_l & ~io_pause_l);
assign iot3x_l = ~(md03_l & ~md04_l & ~md05_l & ~io_pause_l);
assign iot1x_l = ~(md03_l & md04_l & ~md05_l & ~io_pause_l);
assign iot0x_l = ~(md03_l & md04_l & md05_l & ~io_pause_l);
// ic2: sn74138 
assign iot47_l = ~(~md06_l & ~md07_l & ~md08_l & ~iot4x_l & ~io_pause_l);
assign iot46_l = ~(~md06_l & ~md07_l & md08_l & ~iot4x_l & ~io_pause_l);
assign iot45_l = ~(~md06_l & md07_l & ~md08_l & ~iot4x_l & ~io_pause_l);
assign iot44_l = ~(~md06_l & md07_l & md08_l & ~iot4x_l & ~io_pause_l);
assign iot43_l = ~(md06_l & ~md07_l & ~md08_l & ~iot4x_l & ~io_pause_l);
assign iot42_l = ~(md06_l & ~md07_l & md08_l & ~iot4x_l & ~io_pause_l);
assign iot41_l = ~(md06_l & md07_l & ~md08_l & ~iot4x_l & ~io_pause_l);
assign iot40_l = ~(md06_l & md07_l & md08_l & ~iot4x_l & ~io_pause_l);
// ic3: sn74151 
assign tx_sel = ~(~sw4 & ~sw5 & ~sw6
                   | iot04_l & ~sw4 & ~sw5 & sw6
                   | iot41_l & ~sw4 & sw5 & ~sw6
                   | iot43_l & ~sw4 & sw5 & sw6
                   | iot45_l & sw4 & ~sw5 & ~sw6
                   | iot47_l & sw4 & ~sw5 & sw6
                   | iot35_l & sw4 & sw5 & ~sw6
                   | iot12_l & sw4 & sw5 & sw6);
// ic4: sn74151 
assign rx_sel = ~(~sw4 & ~sw5 & ~sw6
                   | iot03_l & ~sw4 & ~sw5 & sw6
                   | iot40_l & ~sw4 & sw5 & ~sw6
                   | iot42_l & ~sw4 & sw5 & sw6
                   | iot44_l & sw4 & ~sw5 & ~sw6
                   | iot46_l & sw4 & ~sw5 & sw6
                   | iot34_l & sw4 & sw5 & ~sw6
                   | iot11_l & sw4 & sw5 & sw6);
// ic5: sn74138 
assign iot04_l = ~(~md06_l & md07_l & md08_l & ~iot0x_l & ~io_pause_l);
assign iot03_l = ~(md06_l & ~md07_l & ~md08_l & ~iot0x_l & ~io_pause_l);
// ic6: sn74138 
assign iot12_l = ~(md06_l & ~md07_l & md08_l & ~iot1x_l & ~io_pause_l);
assign iot11_l = ~(md06_l & md07_l & ~md08_l & ~iot1x_l & ~io_pause_l);
// ic7: sn74138 
assign iot35_l = ~(~md06_l & md07_l & ~md08_l & ~iot3x_l & ~io_pause_l);
assign iot34_l = ~(~md06_l & md07_l & md08_l & ~iot3x_l & ~io_pause_l);
// ic8: sn74151 
assign rx_rate = bd109 & ~sw1 & ~sw2 & ~sw3
                  | bd300 & ~sw1 & ~sw2 & sw3
                  | bd600 & ~sw1 & sw2 & ~sw3
                  | bd1200 & ~sw1 & sw2 & sw3
                  | bd9600 & sw1 & ~sw2 & ~sw3
                  | bd38400 & sw1 & ~sw2 & sw3
                  | bd76800 & sw1 & sw2 & ~sw3
                  | bd153600 & sw1 & sw2 & sw3;
// ic9: sn7411 
assign div11 = n_t_2x & n_t_5x & bd1745;
// ic12: sn7427 
assign is110 = ~(sw1
                  | sw2
                  | sw3);
// r1: r_us_ 
// r2: r_us_ 
// r10: r_us_ 
// r15: r_us_ 
// r20: r_us_ 
// r21: r_us_ 
// r24: r_us_ 
// r26: r_us_ 
// open collector 'wire-or's 
assign c0_l = dokcc? ~dokcc: 1'bz;
assign c1_l = dokrs
               | dokcc? 1'b0: 1'bz;
assign data04_l = (dokrs & rx7)? 1'b0: 1'bz;
assign data05_l = (n_t_34x & dokrs)? 1'b0: 1'bz;
assign data06_l = (dokrs & n_t_36x)? 1'b0: 1'bz;
assign data07_l = (n_t_35x & dokrs)? 1'b0: 1'bz;
assign data08_l = (dokrs & n_t_37x)? 1'b0: 1'bz;
assign data09_l = (n_t_38x & dokrs)? 1'b0: 1'bz;
assign data10_l = (dokrs & n_t_39x)? 1'b0: 1'bz;
assign data11_l = (n_t_40x & dokrs)? 1'b0: 1'bz;
assign int_rqst_l = (flgs & int_enab)? 1'b0: 1'bz;
assign internal_io_l = tx_sel
                        | rx_sel? 1'b0: 1'bz;
assign skip_l = ~(~(n_t_19x & flgs
                   | tkskp))? ~(n_t_19x & flgs
                   | tkskp): 1'bz;
endmodule