Analysis & Synthesis report for warv
Thu Sep 18 07:37:03 2025
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. User-Specified and Inferred Latches
  9. Registers Removed During Synthesis
 10. Analysis & Synthesis Messages
 11. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 18 07:37:03 2025           ;
; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name               ; warv                                            ;
; Top-level Entity Name       ; warv                                            ;
; Family                      ; MAX7000S                                        ;
; Total macrocells            ; 54                                              ;
; Total pins                  ; 64                                              ;
+-----------------------------+-------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Option                                                                     ; Setting         ; Default Value ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Device                                                                     ; EPM7128SLC84-15 ;               ;
; Top-level entity name                                                      ; warv            ; warv          ;
; Family name                                                                ; MAX7000S        ; Cyclone IV GX ;
; Type of Retiming Performed During Resynthesis                              ; Full            ;               ;
; Resynthesis Optimization Effort                                            ; Normal          ;               ;
; Physical Synthesis Level for Resynthesis                                   ; Normal          ;               ;
; Use Generated Physical Constraints File                                    ; On              ;               ;
; Use smart compilation                                                      ; Off             ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On              ; On            ;
; Enable compact report table                                                ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                                        ; Off             ; Off           ;
; Preserve fewer node names                                                  ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                                  ; Off             ; Off           ;
; Verilog Version                                                            ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                               ; VHDL_1993       ; VHDL_1993     ;
; State Machine Processing                                                   ; Auto            ; Auto          ;
; Safe State Machine                                                         ; Off             ; Off           ;
; Extract Verilog State Machines                                             ; On              ; On            ;
; Extract VHDL State Machines                                                ; On              ; On            ;
; Ignore Verilog initial constructs                                          ; Off             ; Off           ;
; Iteration limit for constant Verilog loops                                 ; 5000            ; 5000          ;
; Iteration limit for non-constant Verilog loops                             ; 250             ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On              ; On            ;
; Infer RAMs from Raw Logic                                                  ; On              ; On            ;
; Parallel Synthesis                                                         ; On              ; On            ;
; NOT Gate Push-Back                                                         ; On              ; On            ;
; Power-Up Don't Care                                                        ; On              ; On            ;
; Remove Duplicate Registers                                                 ; On              ; On            ;
; Ignore CARRY Buffers                                                       ; Off             ; Off           ;
; Ignore CASCADE Buffers                                                     ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                      ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                                  ; Off             ; Off           ;
; Ignore LCELL Buffers                                                       ; Auto            ; Auto          ;
; Ignore SOFT Buffers                                                        ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                             ; Off             ; Off           ;
; Optimization Technique                                                     ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                                       ; On              ; On            ;
; Auto Logic Cell Insertion                                                  ; On              ; On            ;
; Parallel Expander Chain Length                                             ; 4               ; 4             ;
; Auto Parallel Expanders                                                    ; On              ; On            ;
; Auto Open-Drain Pins                                                       ; On              ; On            ;
; Auto Resource Sharing                                                      ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell                                               ; 100             ; 100           ;
; Use LogicLock Constraints during Resource Balancing                        ; On              ; On            ;
; Ignore translate_off and synthesis_off directives                          ; Off             ; Off           ;
; Report Parameter Settings                                                  ; On              ; On            ;
; Report Source Assignments                                                  ; On              ; On            ;
; Report Connectivity Checks                                                 ; On              ; On            ;
; HDL message level                                                          ; Level2          ; Level2        ;
; Suppress Register Optimization Related Messages                            ; Off             ; Off           ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000            ; 5000          ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000            ; 5000          ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100             ; 100           ;
; Block Design Naming                                                        ; Auto            ; Auto          ;
; Synthesis Effort                                                           ; Auto            ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On              ; On            ;
; Pre-Mapping Resynthesis Optimization                                       ; Off             ; Off           ;
; Analysis & Synthesis Message Level                                         ; Medium          ; Medium        ;
; Disable Register Merging Across Hierarchies                                ; Auto            ; Auto          ;
; Synthesis Seed                                                             ; 1               ; 1             ;
+----------------------------------------------------------------------------+-----------------+---------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                     ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                       ; Library ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
; warv.v                           ; yes             ; User Verilog HDL File  ; /home/vrs/Eagle/projects/DEC/Mxxx/M885/warv/warv.v ;         ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 54                   ;
; Total registers      ; 20                   ;
; I/O pins             ; 64                   ;
; Shareable expanders  ; 10                   ;
; Maximum fan-out node ; md3_low              ;
; Maximum fan-out      ; 39                   ;
; Total fan-out        ; 516                  ;
; Average fan-out      ; 4.03                 ;
+----------------------+----------------------+


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                 ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |warv                      ; 54         ; 64   ; |warv               ; work         ;
+----------------------------+------------+------+---------------------+--------------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; dk8ie                                              ; GND                 ; yes                    ;
; dk8flg                                             ; GND                 ; yes                    ;
; dk04                                               ; dk03                ; yes                    ;
; Number of user-specified and inferred latches = 3  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; done                                  ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 1 ;                                        ;
+---------------------------------------+----------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Sep 18 07:37:01 2025
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off warv -c warv
Info (12021): Found 1 design units, including 1 entities, in source file warv.v
    Info (12023): Found entity 1: warv
Info (12127): Elaborating entity "warv" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at warv.v(141): object "b_dicd_low" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at warv.v(142): object "b_load_en_low" assigned a value but never read
Warning (10240): Verilog HDL Always Construct warning at warv.v(439): inferring latch(es) for variable "y03", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(439): inferring latch(es) for variable "y02", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(446): inferring latch(es) for variable "x03", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(446): inferring latch(es) for variable "x02", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(453): inferring latch(es) for variable "y07", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(453): inferring latch(es) for variable "y06", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(453): inferring latch(es) for variable "y05", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(453): inferring latch(es) for variable "y04", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable "x07", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable "x06", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable "x05", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(465): inferring latch(es) for variable "x04", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(476): inferring latch(es) for variable "y11", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(476): inferring latch(es) for variable "y10", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(476): inferring latch(es) for variable "y09", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(476): inferring latch(es) for variable "y08", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(487): inferring latch(es) for variable "x11", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(487): inferring latch(es) for variable "x10", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(487): inferring latch(es) for variable "x09", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(487): inferring latch(es) for variable "x08", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(527): inferring latch(es) for variable "int_enable", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(532): inferring latch(es) for variable "device_flag", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(577): inferring latch(es) for variable "dk8ie", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(603): inferring latch(es) for variable "dk04", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at warv.v(639): inferring latch(es) for variable "dk8flg", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "dk8flg" at warv.v(639)
Info (10041): Inferred latch for "dk04" at warv.v(603)
Info (10041): Inferred latch for "dk8ie" at warv.v(577)
Info (10041): Inferred latch for "device_flag" at warv.v(532)
Info (10041): Inferred latch for "int_enable" at warv.v(527)
Info (10041): Inferred latch for "x08" at warv.v(487)
Info (10041): Inferred latch for "x09" at warv.v(487)
Info (10041): Inferred latch for "x10" at warv.v(487)
Info (10041): Inferred latch for "x11" at warv.v(487)
Info (10041): Inferred latch for "y08" at warv.v(476)
Info (10041): Inferred latch for "y09" at warv.v(476)
Info (10041): Inferred latch for "y10" at warv.v(476)
Info (10041): Inferred latch for "y11" at warv.v(476)
Info (10041): Inferred latch for "x04" at warv.v(465)
Info (10041): Inferred latch for "x05" at warv.v(465)
Info (10041): Inferred latch for "x06" at warv.v(465)
Info (10041): Inferred latch for "x07" at warv.v(465)
Info (10041): Inferred latch for "y04" at warv.v(453)
Info (10041): Inferred latch for "y05" at warv.v(453)
Info (10041): Inferred latch for "y06" at warv.v(453)
Info (10041): Inferred latch for "y07" at warv.v(453)
Info (10041): Inferred latch for "x02" at warv.v(446)
Info (10041): Inferred latch for "x03" at warv.v(446)
Info (10041): Inferred latch for "y02" at warv.v(439)
Info (10041): Inferred latch for "y03" at warv.v(439)
Warning (14025): LATCH primitive "device_flag" is permanently disabled
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "dly_done_low" is stuck at VCC
Info (280013): Promoted pin-driven signal(s) to global signal
    Info (280014): Promoted clock signal driven by pin "clock" to global clock signal
Warning (21074): Design contains 6 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "del_1_low"
    Warning (15610): No output dependent on input pin "grn_delay"
    Warning (15610): No output dependent on input pin "ld_del_low"
    Warning (15610): No output dependent on input pin "n_t_35x"
    Warning (15610): No output dependent on input pin "red_delay"
    Warning (15610): No output dependent on input pin "set_done"
Info (21057): Implemented 128 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 27 input pins
    Info (21059): Implemented 25 output pins
    Info (21060): Implemented 12 bidirectional pins
    Info (21063): Implemented 54 macrocells
    Info (21073): Implemented 10 shareable expanders
Info (144001): Generated suppressed messages file /home/vrs/Eagle/projects/DEC/Mxxx/M885/warv/output_files/warv.map.smsg
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 37 warnings
    Info: Peak virtual memory: 564 megabytes
    Info: Processing ended: Thu Sep 18 07:37:03 2025
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/vrs/Eagle/projects/DEC/Mxxx/M885/warv/output_files/warv.map.smsg.


