Date: >LAST_DATE_TIME Sheet: >SHEET REV: TITLE: Document Number: >DRAWING_NAME FRAME DIN A3, landscape with extra doc field Quad-Height DEC board Quad-Height DEC edge connector DV1 DU1 DT1 DS1 DR1 DP1 DN1 DM1 DL1 DK1 DJ1 DH1 DF1 DE1 DD1 DC1 DB1 DA1 DV2 DU2 DT2 DS2 DR2 DP2 DN2 DM2 DL2 DK2 DJ2 DH2 DF2 DE2 DD2 DC2 DB2 DA2 CV1 CU1 CT1 CS1 CR1 CP1 CN1 CM1 CL1 CK1 CJ1 CH1 CF1 CE1 CD1 CC1 CB1 CA1 CV2 CU2 CT2 CS2 CR2 CP2 CN2 CM2 CL2 CK2 CJ2 CH2 CF2 CE2 CD2 CC2 CB2 CA2 BV1 BU1 BT1 BS1 BR1 BP1 BN1 BM1 BL1 BK1 BJ1 BH1 BF1 BE1 BD1 BC1 BB1 BA1 BV2 BU2 BT2 BS2 BR2 BP2 BN2 BM2 BL2 BK2 BJ2 BH2 BF2 BE2 BD2 BC2 BB2 BA2 AV1 AU1 AT1 AS1 AR1 AP1 AN1 AM1 AL1 AK1 AJ1 AH1 AF1 AE1 AD1 AC1 AB1 AA1 AV2 AU2 AT2 AS2 AR2 AP2 AN2 AM2 AL2 AK2 AJ2 AH2 AF2 AE2 AD2 AC2 AB2 AA2 Dual In Line Package >NAME >VALUE 40 pin wide DIP >NAME >VALUE Single-Height DEC board Single-Height DEC board 3 Standard Single-height boards stuck together Double-Height DEC board Double-Height DEC board Dual In Line Package >NAME >VALUE >Value >NAME GND VCC >NAME >VALUE TXD >NAME >NAME >NAME GND >NAME >VALUE Board outlines for DEC boards. Quad-Height DEC board Bus Transceiver IM6100 PDP-8 on a chip. MEDIC MMU/DMA/RTC for IM6100. 512Kx8 Static RAM >VALUE >VALUE SUPPLY SYMBOL SUPPLY SYMBOL Dual In Line Package Small >NAME >VALUE Dual In Line Package >NAME >VALUE >NAME >VALUE >NAME >VALUE MEMORY MEMORY Dual In Line Package >NAME >VALUE >NAME >VALUE >NAME GND VCC MEMORY Dual In Line Package 0.3 inch >NAME >VALUE Dual In Line Package >NAME >VALUE >NAME GND VCC >NAME >VALUE >NAME >VALUE PAL PAL >VALUE >NAME >VALUE >NAME >NAME VCC GND >VALUE >NAME TTL Devices, 74xx Series with US Symbols Based on the following sources: <ul> <li>Texas Instruments TTL Data Book   Volume 1, 1996. <li>TTL Data Book, Volume 2 , 1993 <li>National Seminconductor Databook 1990, ALS/LS Logic <li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 <li>http://icmaster.com/ViewCompare.asp </ul> <author>Created by librarian@cadsoft.de</author> Dual In Line Package >NAME >VALUE Small Outline package 150 mil >VALUE >NAME Leadless Chip Carrier Ceramic Package >NAME >VALUE Dual In Line Package >NAME >VALUE Wide Small Outline package 300 mil >VALUE >NAME >NAME >VALUE >NAME GND VCC >NAME >VALUE >NAME >VALUE >NAME >VALUE >NAME >VALUE >NAME >VALUE >NAME >VALUE Quad 2-input NOR gate Hex INVERTER, open collector Octal BUFFER and LINE DRIVER, 3-state Octal D type transparent LATCH, edge triggered Hex INVERTER Quad 2-input AND gate Dual D type positive edge triggered FLIP FLOP, preset and clear Omnibus Connections DATA Drivers DATA Receivers MD Drivers IOT Support CPU and MMU Timeshare IOTs: CINT = TSIOT & (MA == xxxx1x000100) SINT = TSIOT & (MA == xxxx1x101100) CUF = TSIOT & (MA == xxxx1x110100) SUF = TSIOT & (MA == xxxx1x111100) GTF = TSIOT & (MA == xxxx0x000100) RTF = TSIOT & (MA == xxxx0x000101) CAF = TSIOT & (MA == xxxx0x000111) NDEVSEL = DEVSEL & (MA \!= xxx010101100) # (Inhibits LIF) CPDSPD = TSIOT & (MA = xxxx1x11x110) IFETCH Event Detect (and latch) on rising(XTAFETCH) HLT = (DX == 1111xxxxxx1x0) on rising(XTAFETCH) OSR= (DX == 1111xxxxxxx10) on rising(XTAFETCH) IOT = (DX == 1110xxxxxxxxx) FNOP= PRV & (HLT | OSR | IOT) on rising(XTAFETCH) IBIF = (DX == 10xxxxxxxxxx) XTAFETCH = XTA & IFETCH TSIOT = XTA & DEVSEL & IOT & (MA == xxx0x0xxx1xx) on rising(XTAFETCH) PRV = UF & CPSEL\\ FNOP inhibited when fetching CP memory. MA Latches User Mode CP MMU Support IOT and OSR Inhibit HLT Inhibit Generate timeshare interrupt request. Allow non-bus skip/int requests. Implement CINT Implement SINT Implement GTF Implement RTF Implement CAF Implement Memory Implement Memory Bank disable Implement PDF support. HLT Inhibit (resume) User Mode Trap