`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    17:32:39 10/28/10
// Design Name:    
// Module Name:    seg7
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module seg7(in, out);

input [3:0] in;
output [6:0] out;

assign out = (in == 4'b0000)? 95:
           (in == 4'b0001)? 5:
           (in == 4'b0010)? 118:
           (in == 4'b0011)? 117:
           (in == 4'b0100)? 109:
           (in == 4'b0101)? 121:
           (in == 4'b0110)? 123:
           (in == 4'b0111)? 69:
           (in == 4'b1000)? 127:
           (in == 4'b1001)? 125:
           (in == 4'b1010)? 111:
           (in == 4'b1011)? 59:
           (in == 4'b1100)? 90:
           (in == 4'b1101)? 55:
           (in == 4'b1110)? 126:
                            106;

endmodule