module sheet14(ac00, ac01, ac02, ac03, ac04, ac05, ac06, ac07, ac08, ac09, ac10, ac11, ac_clear, acclr, add_accepted_, bac00, bac01, bac02, bac03, bac04, bac05, bac06, bac07, bac08, bac09, bac10, bac11, badd_accepted_, bbreak, binitialize_, biop1_, biop2_, biop4_, bmb00, bmb01, bmb02, bmb03, bmb03_, bmb04, bmb04_, bmb05, bmb05_, bmb06, bmb06_, bmb07, bmb07_, bmb08, bmb08_, bmb09, bmb10, bmb11, break_, brk_rqst, brq, brun_, bts1, bts3, btt_inst_, bwc_overflow, ca_incr_, ca_increment_, clock_ac_clr_, d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d_in_, da00, da01, da02, da03, da04, da05, da06, da07, da08, da09, da10, da11, data00, data01, data02, data03, data04, data05, data06, data07, data08, data09, data10, data11, data_add00, data_add01, data_add02, data_add03, data_add04, data_add05, data_add06, data_add07, data_add08, data_add09, data_add10, data_add11, data_in_, eda0, eda1, eda2, ext_data_add0, ext_data_add1, ext_data_add2, in00, in01, in02, in03, in04, in05, in06, in07, in08, in09, in10, in11, initialize_, input_bus00, input_bus01, input_bus02, input_bus03, input_bus04, input_bus05, input_bus06, input_bus07, input_bus08, input_bus09, input_bus10, input_bus11, int_rqst, io_bus_in00_, io_bus_in01_, io_bus_in02_, io_bus_in03_, io_bus_in04_, io_bus_in05_, io_bus_in06_, io_bus_in07_, io_bus_in08_, io_bus_in09_, io_bus_in10_, io_bus_in11_, io_bus_in_int_, io_bus_in_skip_, io_skip, iop1_, iop2_, iop4_, irq, line_, line_in, mb00, mb01, mb02, mb03, mb03_, mb04, mb04_, mb05, mb05_, mb06, mb06_, mb07, mb07_, mb08, mb08_, mb09, mb10, mb11, me05_, me06_, me07_, me08_, me09_, me10_, me11_, mem_incr, memory_increment, mp_int_, mp_skip_, n3_cycle, n3cycle, n__200, n__201, n__202, n__203, n__204, n__205, n__206, n__207, n__208, n__209, n__210, n__211, n__212, n__213, n__214, n__215, n__216, n__217, n__218, n__219, n__220, n__221, n__222, n__223, n__243, n__245, n__246, n__250, n__253, n__254, n__259, n__260, n__261, nc, run_, skipb, ts1_, ts3_, tt0_, tt1_, tt2_, tt3_, tt4_, tt5_, tt6_, tt7_, tt_ac_clr_, tt_inst_, tt_int_, tt_skip_, wc_overflow_, dclk);
input dclk;
// synthesis attribute CLOCK_SIGNAL of dclk is "yes";
input ac00;
input ac01;
input ac02;
input ac03;
input ac04;
input ac05;
input ac06;
input ac07;
input ac08;
input ac09;
input ac10;
input ac11;
output ac_clear;
input acclr;
input add_accepted_;
output wand bac00;
output wand bac01;
output wand bac02;
output wand bac03;
output wand bac04;
output wand bac05;
output wand bac06;
output wand bac07;
output wand bac08;
output wand bac09;
output wand bac10;
output wand bac11;
output wand badd_accepted_;
output wand bbreak;
output wand binitialize_;
output wand biop1_;
output wand biop2_;
output wand biop4_;
output wand bmb00;
output wand bmb01;
output wand bmb02;
output wand bmb03;
output wand bmb03_;
output wand bmb04;
output wand bmb04_;
output wand bmb05;
output wand bmb05_;
output wand bmb06;
output wand bmb06_;
output wand bmb07;
output wand bmb07_;
output wand bmb08;
output wand bmb08_;
output wand bmb09;
output wand bmb10;
output wand bmb11;
input break_;
output brk_rqst;
input brq;
output wand brun_;
output wand bts1;
output wand bts3;
output wand btt_inst_;
output wand bwc_overflow;
input ca_incr_;
output ca_increment_;
input clock_ac_clr_;
input d00;
input d01;
input d02;
input d03;
input d04;
input d05;
input d06;
input d07;
input d08;
input d09;
input d10;
input d11;
input d_in_;
input da00;
input da01;
input da02;
input da03;
input da04;
input da05;
input da06;
input da07;
input da08;
input da09;
input da10;
input da11;
output data00;
output data01;
output data02;
output data03;
output data04;
output data05;
output data06;
output data07;
output data08;
output data09;
output data10;
output data11;
output data_add00;
output data_add01;
output data_add02;
output data_add03;
output data_add04;
output data_add05;
output data_add06;
output data_add07;
output data_add08;
output data_add09;
output data_add10;
output data_add11;
output data_in_;
input eda0;
input eda1;
input eda2;
output ext_data_add0;
output ext_data_add1;
output ext_data_add2;
input in00;
input in01;
input in02;
input in03;
input in04;
input in05;
input in06;
input in07;
input in08;
input in09;
input in10;
input in11;
input initialize_;
output input_bus00;
output input_bus01;
output input_bus02;
output input_bus03;
output input_bus04;
output input_bus05;
output input_bus06;
output input_bus07;
output input_bus08;
output input_bus09;
output input_bus10;
output input_bus11;
output int_rqst;
input io_bus_in00_;
input io_bus_in01_;
input io_bus_in02_;
input io_bus_in03_;
input io_bus_in04_;
input io_bus_in05_;
input io_bus_in06_;
input io_bus_in07_;
input io_bus_in08_;
input io_bus_in09_;
input io_bus_in10_;
input io_bus_in11_;
input io_bus_in_int_;
input io_bus_in_skip_;
output io_skip;
input iop1_;
input iop2_;
input iop4_;
input irq;
output line_;
input line_in;
input mb00;
input mb01;
input mb02;
input mb03;
input mb03_;
input mb04;
input mb04_;
input mb05;
input mb05_;
input mb06;
input mb06_;
input mb07;
input mb07_;
input mb08;
input mb08_;
input mb09;
input mb10;
input mb11;
input me05_;
input me06_;
input me07_;
input me08_;
input me09_;
input me10_;
input me11_;
input mem_incr;
output memory_increment;
input mp_int_;
input mp_skip_;
output n3_cycle;
input n3cycle;
input n__200;
input n__201;
input n__202;
input n__203;
input n__204;
input n__205;
input n__206;
input n__207;
input n__208;
input n__209;
input n__210;
input n__211;
input n__212;
input n__213;
input n__214;
input n__215;
input n__216;
input n__217;
input n__218;
input n__219;
input n__220;
input n__221;
input n__222;
input n__223;
input n__243;
input n__245;
input n__246;
input n__250;
input n__253;
input n__254;
input n__259;
input n__260;
input n__261;
input nc;
input run_;
input skipb;
input ts1_;
input ts3_;
input tt0_;
input tt1_;
input tt2_;
input tt3_;
input tt4_;
input tt5_;
input tt6_;
input tt7_;
input tt_ac_clr_;
input tt_inst_;
input tt_int_;
input tt_skip_;
input wc_overflow_;

// Sheet 14
assign bac00 = ac00;
assign bac01 = ac01;
assign bac02 = ac02;
assign bac03 = ac03;
assign bac04 = ac04;
assign bac05 = ac05;
assign bac06 = ac06;
assign bac07 = ac07;
assign bac08 = ac08;
assign bac09 = ac09;
assign bac10 = ac10;
assign bac11 = ac11;
assign biop1_ = iop1_;
assign biop2_ = iop2_;
assign biop4_ = iop4_;
assign bts3 = ts3_;
assign bts1 = ts1_;
assign binitialize_ = initialize_;
assign bmb00 = mb00;
assign bmb01 = mb01;
assign bmb02 = mb02;
assign bmb03_ = mb03_;
assign bmb03 = mb03;
assign bmb04_ = mb04_;
assign bmb04 = mb04;
assign bmb05_ = mb05_;
assign bmb05 = mb05;
assign bmb06_ = mb06_;
assign bmb06 = mb06;
assign bmb07_ = mb07_;
assign bmb07 = mb07;
assign bmb08_ = mb08_;
assign bmb08 = mb08;
assign bmb09 = mb09;
assign bmb10 = mb10;
assign bmb11 = mb11;
assign brun_ = run_;
assign btt_inst_ = tt_inst_;
assign bwc_overflow = wc_overflow_;
assign bbreak = break_;
assign badd_accepted_ = add_accepted_ & ts1_;
assign input_bus00 = ~(in00 & io_bus_in00_);
assign input_bus02 = ~(in02 & io_bus_in02_);
assign input_bus04 = ~(in04 & io_bus_in04_ & tt0_);
assign input_bus01 = ~(in01 & io_bus_in01_);
assign input_bus03 = ~(in03 & io_bus_in03_);
assign input_bus05 = ~(in05 & io_bus_in05_ & tt1_ & me05_);
assign input_bus06 = ~(in06 & io_bus_in06_ & tt2_ & me06_);
assign input_bus08 = ~(in08 & io_bus_in08_ & tt4_ & me08_);
assign input_bus10 = ~(in10 & io_bus_in10_ & tt6_ & me10_);
assign input_bus07 = ~(in07 & io_bus_in07_ & tt3_ & me07_);
assign input_bus09 = ~(in09 & io_bus_in09_ & tt5_ & me09_);
assign input_bus11 = ~(in11 & io_bus_in11_ & tt7_ & me11_);
assign io_skip = ~(skipb & io_bus_in_skip_ & tt_skip_ & mp_skip_);
assign ac_clear = ~(acclr & nc & tt_ac_clr_ & clock_ac_clr_);
assign brk_rqst = ~(brq & n__246 & n__246 & n__246);
assign int_rqst = ~(irq & io_bus_in_int_ & tt_int_ & mp_int_);
assign line_ = ~(line_in & n__243 & n__243 & n__243);
assign data_in_ = ~(d_in_ & n__245 & n__245 & n__245);
assign data_add00 = ~(da00 & n__202 & n__202 & n__202);
assign data_add02 = ~(da02 & n__203 & n__203 & n__203);
assign data_add04 = ~(da04 & n__201 & n__201 & n__201);
assign data_add01 = ~(da01 & n__200 & n__200 & n__200);
assign data_add03 = ~(da03 & n__204 & n__204 & n__204);
assign data_add05 = ~(da05 & n__205 & n__205 & n__205);
assign data_add06 = ~(da06 & n__207 & n__207 & n__207);
assign data_add08 = ~(da08 & n__209 & n__209 & n__209);
assign data_add10 = ~(da10 & n__206 & n__206 & n__206);
assign data_add07 = ~(da07 & n__208 & n__208 & n__208);
assign data_add09 = ~(da09 & n__210 & n__210 & n__210);
assign data_add11 = ~(da11 & n__211 & n__211 & n__211);
assign data00 = ~(d00 & n__223 & n__223 & n__223);
assign data02 = ~(d02 & n__221 & n__221 & n__221);
assign data04 = ~(d04 & n__219 & n__219 & n__219);
assign data01 = ~(d01 & n__222 & n__222 & n__222);
assign data03 = ~(d03 & n__220 & n__220 & n__220);
assign data05 = ~(d05 & n__218 & n__218 & n__218);
assign data06 = ~(d06 & n__217 & n__217 & n__217);
assign data08 = ~(d08 & n__215 & n__215 & n__215);
assign data10 = ~(d10 & n__213 & n__213 & n__213);
assign data07 = ~(d07 & n__216 & n__216 & n__216);
assign data09 = ~(d09 & n__214 & n__214 & n__214);
assign data11 = ~(d11 & n__212 & n__212 & n__212);
assign memory_increment = ~(mem_incr & n__250 & n__250 & n__250);
assign ca_increment_ = ~(ca_incr_ & n__254 & n__254 & n__254);
assign ext_data_add1 = ~(eda1 & n__259 & n__259 & n__259);
assign n3_cycle = ~(n3cycle & n__253 & n__253 & n__253);
assign ext_data_add0 = ~(eda0 & n__260 & n__260 & n__260);
assign ext_data_add2 = ~(eda2 & n__261 & n__261 & n__261);

endmodule