module sheet18(mem00, mem01, mem02, mem03, mem04, mem05, mem06, mem07, mem08, mem09, mem10, mem11, mem_p, dclk);
input dclk;
// synthesis attribute CLOCK_SIGNAL of dclk is "yes";
input mem00;
input mem01;
input mem02;
input mem03;
input mem04;
input mem05;
input mem06;
input mem07;
input mem08;
input mem09;
input mem10;
input mem11;
input mem_p;

// Sheet 18

endmodule