module sheet29(b_c_, b_dc_inst, b_fetch, b_line_hold_, b_mem_to_lsr, b_r0_, bstlr, btp3, c, c_, c_no_shift_, c_set_, csr_enable_, dc_inst_, hs, hs_, iot, lh_to_hs, lhs, lhs_, line_, line_hold_, manual_preset_, mb03, mb04_, mb05_, mb06_, mb07_, mb08_, mb09, mb10, mb11, mb11_, mem00, mem09, mem_done_, mem_inh9_11_, mem_to_lsr_, n__725, n__726, n__727, n__728, n__729, n__730, n__731, n__732, n__733, n__742, n__743, n__744, n__745, n__746, n__747, r0, r0_, s, s_, s_set_, store_, tp3, tp4, ts1, ts2, ts3, tt_ac_load_, tt_carry_insert, tt_carry_insert_, tt_carry_insert_c_, tt_carry_insert_s, tt_carry_insert_s_, tt_cycle_, tt_data, tt_increment_, tt_inst, tt_inst_, tt_io_enable_, tt_l_disable, tt_line_shift_, tt_right_shift_enable, tt_right_shift_enable_, tt_set_, tt_shift_enable, tt_shift_enable_, dclk);
input dclk;
// synthesis attribute CLOCK_SIGNAL of dclk is "yes";
output wand b_c_;
output b_dc_inst;
input b_fetch;
output wand b_line_hold_;
output b_mem_to_lsr;
input b_r0_;
output wand bstlr;
output btp3;
inout c;
output reg c_;
output c_no_shift_;
inout c_set_;
inout csr_enable_;
inout dc_inst_;
output reg hs;
inout hs_;
input iot;
input lh_to_hs;
inout lhs;
input lhs_;
input line_;
inout line_hold_;
input manual_preset_;
input mb03;
input mb04_;
input mb05_;
input mb06_;
input mb07_;
input mb08_;
input mb09;
input mb10;
input mb11;
input mb11_;
input mem00;
input mem09;
input mem_done_;
inout mem_inh9_11_;
input mem_to_lsr_;
inout n__725;
inout n__726;
inout n__727;
inout n__728;
inout n__729;
inout n__730;
inout n__731;
inout n__732;
inout n__733;
inout n__742;
inout n__743;
inout n__744;
inout n__745;
inout n__746;
inout n__747;
inout r0;
inout r0_;
inout s;
output reg s_;
inout s_set_;
inout store_;
input tp3;
input tp4;
input ts1;
input ts2;
input ts3;
output tt_ac_load_;
inout tt_carry_insert;
output tt_carry_insert_;
inout tt_carry_insert_c_;
output tt_carry_insert_s;
inout tt_carry_insert_s_;
output tt_cycle_;
output tt_data;
output tt_increment_;
inout tt_inst;
inout tt_inst_;
inout tt_io_enable_;
inout tt_l_disable;
inout tt_line_shift_;
inout tt_right_shift_enable;
inout tt_right_shift_enable_;
output tt_set_;
inout tt_shift_enable;
output tt_shift_enable_;

// Sheet 29
assign b_line_hold_ = line_hold_;
assign b_c_ = c_;
assign bstlr = mem_done_ & s & ts1;
assign btp3 = ~(tp3);
assign b_mem_to_lsr = ~(mem_to_lsr_);
assign b_dc_inst = ~(dc_inst_);
assign n__728 = ~(mem00 & hs_);
assign n__729 = ~(n__728);
assign tt_shift_enable_ = ~(tt_shift_enable);
assign n__727 = ~(n__726);
assign tt_carry_insert_ = ~(tt_carry_insert);
assign tt_shift_enable = ~(tt_line_shift_ & tt_right_shift_enable_);
assign mem_inh9_11_ = ~(n__729 & n__727);
assign r0_ = ~(r0);
assign tt_carry_insert_s = ~(tt_carry_insert_s_);
assign tt_set_ = ~(n__731);
assign tt_right_shift_enable_ = ~(tt_right_shift_enable);
assign n__733 = ~(n__742);
assign tt_cycle_ = ~(tt_l_disable & tt_inst_);
assign n__746 = ~(line_ & s);
assign tt_inst = ~(tt_inst_);
assign n__744 = ~(n__743);
assign tt_data = ~(n__746 & n__747);
assign n__747 = ~(c & n__745);
assign n__745 = ~(line_);
assign n__731 = ~(c_set_ & s_set_);
assign n__730 = ~(c & hs_ & ts2);
assign tt_io_enable_ = ~(ts3 & mb09 & tt_inst);
assign n__742 = ~(mb03 & mb04_ & mb05_);
assign tt_right_shift_enable = ~(n__730 & csr_enable_ & tt_io_enable_);
assign tt_line_shift_ = ~(ts2 & n__728 & s);
assign tt_carry_insert_s_ = ~(ts3 & s & c_set_);
assign n__743 = ~(mb06_ & mb07_ & mb08_);
assign lhs = ~(lhs_ & lhs_ & lhs_ & lhs_);
assign r0 = ~(b_r0_ & b_r0_ & b_r0_ & b_r0_);
assign c_no_shift_ = ~(n__725 & hs);
assign csr_enable_ = ~(n__725 & hs_);
assign n__725 = ~(store_);
assign n__726 = ~(s & ts2 & mem09);
assign dc_inst_ = ~(n__733 & iot);
assign tt_carry_insert = ~(tt_carry_insert_c_ & tt_carry_insert_s_ & line_hold_);
assign n__732 = ~(store_ & tt_io_enable_);
assign tt_carry_insert_c_ = ~(ts3 & c & mb11_);
assign tt_l_disable = ~(c_ & tt_inst_ & s_);
assign tt_ac_load_ = ~(n__732 & tp3);
assign s_set_ = ~(tt_inst & mb10);
assign tt_increment_ = ~(ts2 & n__729 & mem_inh9_11_ & s);
assign store_ = ~(r0_ & c & ts3 & mb11);
assign c_set_ = ~(s & mb10 & mb11_);
assign tt_inst_ = ~(iot & n__733 & n__744 & b_fetch);
assign line_hold_ = ~(r0 & c & ts3 & mb11);
always @(posedge tp4, negedge manual_preset_) begin
  if (~manual_preset_)
    s_ <= 1'b1;
  else
    s_ <= s_set_;
end
assign s = ~s_;
always @(posedge tp4, negedge manual_preset_) begin
  if (~manual_preset_)
    c_ <= 1'b1;
  else
    c_ <= c_set_;
end
assign c = ~c_;
always @(posedge lh_to_hs) begin
    hs <= lhs;
end
assign hs_ = ~hs;

endmodule