module sheet31(mem00, mem01, mem02, mem03, mem04, mem05, mem06, mem07, mem08, mem09, mem10, mem11, mem_p, mem_parity_even_, n__702, n__703, n__704, n__705, n__706, n__707, n__708, n__709, n__710, n__711, n__712, n__713, n__714, n__715, n__716, n__717, n__718, n__719, n__720, dclk);
input dclk;
// synthesis attribute CLOCK_SIGNAL of dclk is "yes";
input mem00;
input mem01;
input mem02;
input mem03;
input mem04;
input mem05;
input mem06;
input mem07;
input mem08;
input mem09;
input mem10;
input mem11;
input mem_p;
output mem_parity_even_;
inout n__702;
inout n__703;
inout n__704;
inout n__705;
inout n__706;
inout n__707;
inout n__708;
inout n__709;
inout n__710;
inout n__711;
inout n__712;
inout n__713;
inout n__714;
inout n__715;
inout n__716;
inout n__717;
inout n__718;
inout n__719;
inout n__720;

// Sheet 31
assign n__703 =  n__716 ^ n__713 ^ n__714 ^ n__715 ^ mem00 ^ mem01 ^ mem02 ^ mem03;
assign n__702 =  ~n__703;
assign n__707 =  n__718 ^ n__717 ^ n__712 ^ n__719 ^ mem08 ^ mem09 ^ mem10 ^ mem11;
assign n__706 =  ~n__707;
assign mem_parity_even =  n__702 ^ n__704 ^ n__706 ^ n__720 ^ n__703 ^ n__705 ^ n__707 ^ mem_p;
assign mem_parity_even_ =  ~mem_parity_even;
assign n__705 =  n__710 ^ n__709 ^ n__708 ^ n__711 ^ mem04 ^ mem05 ^ mem06 ^ mem07;
assign n__704 =  ~n__705;
assign n__715 = ~(mem03);
assign n__714 = ~(mem02);
assign n__716 = ~(mem00);
assign n__708 = ~(mem06);
assign n__710 = ~(mem04);
assign n__713 = ~(mem01);
assign n__711 = ~(mem07);
assign n__709 = ~(mem05);
assign n__719 = ~(mem11);
assign n__712 = ~(mem10);
assign n__717 = ~(mem09);
assign n__718 = ~(mem08);
assign n__720 = ~(mem_p);

endmodule