module sheet5(ac_clear, ac_clear_, ac_enable, ac_to_mq_enable_, acbar_enable, add_, and_enable_, b_execute, b_fetch, break, break_ok, current_address, d_set_, data_add_enable, data_enable, data_in, data_in_, dca, defer, e_set_, eae_ac_enable_, eae_acbar_enable_, eae_e_set_, eae_l_disable, eae_mem_enable_, f_set_, int_ok_, int_skip_enable_, io_enable, io_on, io_pc_enable_, iop124_, iop1_, iop2_, iop4_, ipc_enable, jmp, jmp_, jms, key_dp, key_exdp, key_la, key_lamfts0_, key_st, key_stexdp, l_enable, lbar_enable, ma_enable0_4, ma_enable5_11, mb03, mb03_, mb04, mb04_, mb05, mb05_, mb06, mb06_, mb07, mb07_, mb09, mb11_, mem_enable0_4, mem_enable0_4_, mem_enable5_8, mem_enable9_11, mem_ext_io_enable_, mem_inh9_11_, mfts0, mfts1, mfts2, mfts3, n__120, n__57, n__58, n__60, n__61, n__62, n__63, n__64, n__65, n__66, n__67, n__68, n__69, n__70, n__71, n__72, n__73, n__74, n__749, n__76, n__79, n__84, op1, op2, opr, osr_, pc_enable, pc_enable_, pc_increment, restart_, sr_enable, store_, tad, ts1, ts2, ts3, ts4, tt_carry_insert_, tt_io_enable_, tt_l_disable, tt_set_, uf_, word_count, dclk);
input dclk;
// synthesis attribute CLOCK_SIGNAL of dclk is "yes";
input ac_clear;
inout ac_clear_;
output wand ac_enable;
input ac_to_mq_enable_;
output wand acbar_enable;
inout add_;
input and_enable_;
input b_execute;
input b_fetch;
input break;
input break_ok;
input current_address;
input d_set_;
output wand data_add_enable;
output wand data_enable;
inout data_in;
input data_in_;
input dca;
input defer;
input e_set_;
input eae_ac_enable_;
input eae_acbar_enable_;
input eae_e_set_;
input eae_l_disable;
input eae_mem_enable_;
input f_set_;
input int_ok_;
inout int_skip_enable_;
inout wand io_enable;
input io_on;
inout io_pc_enable_;
inout iop124_;
input iop1_;
input iop2_;
input iop4_;
inout ipc_enable;
input jmp;
input jmp_;
input jms;
input key_dp;
input key_exdp;
input key_la;
inout key_lamfts0_;
input key_st;
input key_stexdp;
output l_enable;
output lbar_enable;
output wand ma_enable0_4;
output wand ma_enable5_11;
input mb03;
input mb03_;
input mb04;
input mb04_;
input mb05;
input mb05_;
input mb06;
input mb06_;
input mb07;
input mb07_;
input mb09;
input mb11_;
inout wand mem_enable0_4;
inout mem_enable0_4_;
inout wand mem_enable5_8;
output mem_enable9_11;
input mem_ext_io_enable_;
input mem_inh9_11_;
input mfts0;
input mfts1;
input mfts2;
input mfts3;
inout n__120;
inout n__57;
inout n__58;
inout n__60;
inout n__61;
inout n__62;
inout n__63;
inout n__64;
inout n__65;
inout n__66;
inout n__67;
inout n__68;
inout n__69;
inout n__70;
inout n__71;
inout n__72;
inout n__73;
inout n__74;
inout n__749;
inout n__76;
inout n__79;
inout n__84;
input op1;
inout op2;
input opr;
inout osr_;
output wand pc_enable;
inout pc_enable_;
input pc_increment;
input restart_;
output wand sr_enable;
input store_;
input tad;
input ts1;
input ts2;
input ts3;
input ts4;
input tt_carry_insert_;
input tt_io_enable_;
input tt_l_disable;
input tt_set_;
input uf_;
input word_count;

// Sheet 5
assign n__70 = ~(n__63 & uf_);
assign n__63 = ~(osr_);
assign n__58 = ~(mem_enable5_8 & mem_inh9_11_);
assign io_pc_enable_ = ~(iop124_ & io_on);
assign iop124_ = ~(n__120);
assign n__64 = ~(restart_ & mfts1 & key_stexdp);
assign l_enable = (mb05_ & op1 & mb07) | (mfts2 & key_st) | (tt_l_disable) | (eae_l_disable) | (mb05 & op1 & mb07_);
assign n__57 = (ts3 & defer & jmp) | (ts2 & n__68) | (1'b0) | (ts4 & current_address) | (ts4 & defer & jmp_);
assign n__68 = (b_execute & jms) | (dca & b_execute) | (break & data_in) | (mfts3 & key_dp);
assign n__62 = (1'b0) | (ts1 & pc_increment) | (ts4 & word_count) | (mfts2 & key_exdp) | (ts3 & b_execute & jms);
assign n__79 = (op2 & ac_to_mq_enable_ & mb04_) | (io_enable & ac_clear_) | (op1 & n__84) | (ts2 & b_execute & dca);
assign n__84 = (mb04_ & mb06) | (mb04 & mb06_);
assign ac_enable = ~(and_enable_ & n__79 & add_ & eae_ac_enable_);
assign acbar_enable = ~(n__72 & eae_acbar_enable_);
assign ipc_enable = ~(io_pc_enable_ & n__64 & int_skip_enable_ & pc_enable_ & tt_carry_insert_);
assign n__120 = ~(iop1_ & iop2_ & iop4_);
assign mem_enable9_11 = ~(n__58 & eae_mem_enable_ & n__61 & n__73);
assign n__749 = ~(ipc_enable);
assign n__61 = ~(ts3 & jmp & b_fetch & mb03_);
assign n__76 = ~(opr & ts3 & b_fetch & mb03);
assign n__73 = ~(ts4 & n__60 & int_ok_ & pc_enable_);
assign add_ = ~(tad & ts3 & b_execute);
assign int_skip_enable_ = ~(ts2 & b_execute & jms);
assign n__67 = ~(ts2 & break & data_in);
assign n__74 = ~(mem_enable5_8 & mem_enable0_4_ & mb04);
assign n__65 = ~(f_set_ & eae_e_set_ & tt_set_);
assign osr_ = ~(op2 & mb11_ & mb09);
assign mem_enable0_4_ = ~(mem_enable0_4);
assign n__60 = ~(d_set_ & e_set_);
assign op2 = ~(n__76);
assign n__69 = ~(ts4 & break_ok);
assign n__71 = ~(key_dp & mfts3);
assign data_in = ~(data_in_);
assign ac_clear_ = ~(ac_clear);
assign lbar_enable = ~(n__66 & eae_acbar_enable_);
assign key_lamfts0_ = ~(key_la & mfts0);
assign n__66 = ~(op1 & mb07);
assign pc_enable = ~(n__749);
assign data_enable = ~(n__67);
assign sr_enable = ~(n__71 & n__70 & key_lamfts0_);
assign io_enable = ~(iop124_ & mem_ext_io_enable_ & tt_io_enable_);
assign data_add_enable = ~(n__69);
assign mem_enable0_4 = ~(add_ & n__57 & store_ & eae_mem_enable_);
assign ma_enable0_4 = ~(n__74 & n__62);
assign mem_enable5_8 = ~(eae_mem_enable_ & n__61 & mem_enable0_4_ & n__73);
assign ma_enable5_11 = ~(n__62);
assign pc_enable_ = ~(ts4 & n__65);
assign n__72 = ~(op1 & mb06);

endmodule