module sheet6(and_enable, and_enable_, and_h, auto_index_, b_execute, b_fetch, break, c_no_shift_, ca_increment, ca_increment_, carry_insert_, current_address, defer, double_left_rotate, double_right_rotate, eae_execute_, eae_left_shift_enable_, eae_no_shift_enable, eae_right_shift_enable_, fetch_, int_skip_enable_, io_pc_enable_, isz, jms, key_exdp, left_shift, ma00_, ma01_, ma02_, ma03_, ma04_, ma05_, ma06_, ma07_, ma08, mb03_, mb08, mb08_, mb09, mb09_, mb10, mb10_, mb11, mem_enable0_4, memory_increment, mfts2, n__75, n__77, n__78, n__80, n__81, n__82, n__83, n__85, n__86, n__87, n__88, n__89, n__90, n__91, n__92, n__94, no_shift, op1, op1_, opr, pc_enable_, pc_increment, right_shift, skip_or, ts1, ts2, ts3, tt_carry_insert_, tt_cycle_, tt_increment_, tt_right_shift_enable_, tt_shift_enable_, word_count, dclk);
input dclk;
// synthesis attribute CLOCK_SIGNAL of dclk is "yes";
output wand and_enable;
inout and_enable_;
input and_h;
inout auto_index_;
input b_execute;
input b_fetch;
input break;
input c_no_shift_;
inout ca_increment;
input ca_increment_;
output carry_insert_;
input current_address;
input defer;
output wand double_left_rotate;
output wand double_right_rotate;
input eae_execute_;
input eae_left_shift_enable_;
input eae_no_shift_enable;
input eae_right_shift_enable_;
input fetch_;
input int_skip_enable_;
input io_pc_enable_;
input isz;
input jms;
input key_exdp;
output wand left_shift;
input ma00_;
input ma01_;
input ma02_;
input ma03_;
input ma04_;
input ma05_;
input ma06_;
input ma07_;
input ma08;
input mb03_;
input mb08;
input mb08_;
input mb09;
input mb09_;
input mb10;
input mb10_;
input mb11;
input mem_enable0_4;
input memory_increment;
input mfts2;
inout n__75;
inout n__77;
inout n__78;
inout n__80;
inout n__81;
inout n__82;
inout n__83;
inout n__85;
inout n__86;
inout n__87;
inout n__88;
inout n__89;
inout n__90;
inout n__91;
inout n__92;
inout n__94;
output wand no_shift;
inout op1;
inout op1_;
input opr;
input pc_enable_;
inout pc_increment;
output wand right_shift;
input skip_or;
input ts1;
input ts2;
input ts3;
input tt_carry_insert_;
input tt_cycle_;
input tt_increment_;
input tt_right_shift_enable_;
input tt_shift_enable_;
input word_count;

// Sheet 6
assign n__82 = (ts2 & b_execute & isz) | (ts1 & pc_increment) | (op1 & mb11) | (n__80 & skip_or) | (ts3 & b_execute & jms);
assign n__81 = (word_count) | (mfts2 & key_exdp) | (ca_increment & current_address) | (ts2 & memory_increment & break);
assign double_right_rotate = ~(n__94);
assign right_shift = ~(tt_right_shift_enable_ & n__91 & eae_right_shift_enable_);
assign no_shift = ~(n__88 & n__83 & tt_carry_insert_ & c_no_shift_);
assign double_left_rotate = ~(n__90);
assign left_shift = ~(n__92 & eae_left_shift_enable_);
assign and_enable = ~(and_enable_);
assign n__80 = ~(int_skip_enable_ & io_pc_enable_ & pc_enable_);
assign n__83 = ~(op1_ & tt_shift_enable_ & eae_no_shift_enable);
assign n__77 = ~(ma04_ & ma05_ & ma06_ & ma07_);
assign n__78 = ~(ma00_ & ma01_ & ma02_ & ma03_);
assign op1 = ~(op1_);
assign ca_increment = ~(ca_increment_);
assign n__86 = ~(n__77 & tt_increment_);
assign n__75 = ~(ma08 & defer);
assign n__87 = ~(n__78 & tt_increment_);
assign n__85 = ~(n__75 & tt_increment_);
assign n__90 = ~(mb09 & op1 & mb10);
assign n__91 = ~(mb08 & op1 & mb10_);
assign n__88 = ~(mb08_ & op1 & mb09_);
assign and_enable_ = ~(and_h & ts3 & b_execute);
assign n__94 = ~(mb08 & op1 & mb10);
assign n__92 = ~(mb09 & op1 & mb10_);
assign auto_index_ = ~(n__87 & n__86 & n__85 & mem_enable0_4);
assign n__89 = ~(auto_index_ & n__82 & n__81 & tt_carry_insert_);
assign op1_ = ~(opr & ts3 & b_fetch & mb03_);
assign pc_increment = ~(fetch_ & eae_execute_ & tt_cycle_);
assign carry_insert_ = ~(n__89);

endmodule