module sheet7(ac00, ac00_, ac01_, ac02_, ac03_, ac04_, ac05_, ac06_, ac07_, ac08_, ac09_, ac10_, ac11_, ac_load, and_, b_execute, b_fetch, carry_out0, dca_, defer, eae_tp_, io_enable, io_pc_load, io_skip, io_strobe, iot, isz, jmp, jms, key_laexdp, key_st, key_stexdp, link, low_ac0, ma_load, mb03_, mb05, mb06, mb07, mb08, mb08_, mb11_, mb_load, mem_ext_ac_load_enable_, mftp1, mftp2, mid_ac0, n__10, n__100, n__101, n__102, n__103, n__104, n__105, n__106, n__107, n__108, n__109, n__110, n__111, n__112, n__113, n__115, n__93, n__95, n__96, n__97, n__98, n__99, op2, opr, pc_increment, pc_load, pc_load_, skip_, tad_, tp1, tp2, tp2e_, tp3, tp4, ts2, tt_ac_load_, tt_carry_insert, dclk);
input dclk;
// synthesis attribute CLOCK_SIGNAL of dclk is "yes";
input ac00;
input ac00_;
input ac01_;
input ac02_;
input ac03_;
input ac04_;
input ac05_;
input ac06_;
input ac07_;
input ac08_;
input ac09_;
input ac10_;
input ac11_;
output wand ac_load;
input and_;
input b_execute;
input b_fetch;
input carry_out0;
input dca_;
input defer;
input eae_tp_;
input io_enable;
input io_pc_load;
input io_skip;
input io_strobe;
input iot;
input isz;
input jmp;
input jms;
input key_laexdp;
input key_st;
input key_stexdp;
input link;
inout low_ac0;
output wand ma_load;
input mb03_;
input mb05;
input mb06;
input mb07;
input mb08;
input mb08_;
input mb11_;
output wand mb_load;
input mem_ext_ac_load_enable_;
input mftp1;
input mftp2;
inout mid_ac0;
inout n__10;
inout n__100;
inout n__101;
inout n__102;
inout n__103;
inout n__104;
inout n__105;
inout n__106;
inout n__107;
inout n__108;
inout n__109;
inout n__110;
inout n__111;
inout n__112;
inout n__113;
inout n__115;
inout n__93;
inout n__95;
inout n__96;
inout n__97;
inout n__98;
inout n__99;
input op2;
input opr;
input pc_increment;
inout wand pc_load;
inout pc_load_;
output reg skip_;
input tad_;
input tp1;
input tp2;
inout tp2e_;
input tp3;
input tp4;
input ts2;
input tt_ac_load_;
input tt_carry_insert;

// Sheet 7
always @(posedge n__111, negedge b_power_clear_, negedge pc_load_) begin
  if (~b_power_clear_)
    skip_ <= 1'b0;
  else
  if (~pc_load_)
    skip_ <= 1'b1;
  else
    skip_ <= n__108;
end
assign n__104 = ~(ac00 & mb05);
assign mid_ac0 = ~(n__99);
assign n__103 = ~(n__100);
assign low_ac0 = ~(n__98);
assign n__102 = ~(link & mb07);
assign n__105 = ~(n__104 & n__101 & n__102);
assign n__111 = ~(n__113 & tp2e_ & n__115);
assign n__107 = ~(mb11_ & n__105 & op2);
assign n__113 = ~(tp3 & b_fetch & opr);
assign n__96 = (tp3 & jmp & mb03_ & b_fetch) | (tp1 & pc_increment) | (tp3 & tt_carry_insert) | (mftp2 & key_laexdp) | (tp3 & defer & jmp);
assign n__95 = (tp3 & n__93 & b_execute) | (mftp2 & key_st) | (io_strobe & iot) | (tp3 & b_fetch & opr);
assign n__108 = (ts2 & b_execute & carry_out0 & isz) | (io_enable & io_skip) | (n__106 & mb08_) | (n__107 & op2 & mb08 & mb11_);
assign ma_load = ~(n__110 & n__109);
assign mb_load = ~(n__112);
assign pc_load = ~(n__10 & n__96 & n__97);
assign ac_load = ~(eae_tp_ & n__95 & tt_ac_load_ & mem_ext_ac_load_enable_);
assign n__101 = ~(n__103 & mid_ac0 & low_ac0 & mb06);
assign n__99 = ~(ac04_ & ac05_ & ac06_ & ac07_);
assign n__100 = ~(ac00_ & ac01_ & ac02_ & ac03_);
assign n__98 = ~(ac08_ & ac09_ & ac10_ & ac11_);
assign pc_load_ = ~(pc_load);
assign n__106 = ~(n__107);
assign tp2e_ = ~(tp2 & b_execute);
assign n__115 = ~(io_strobe & skip_);
assign n__97 = ~(tp3 & b_execute & jms);
assign n__93 = ~(and_ & tad_ & dca_);
assign n__110 = ~(mftp1 & key_stexdp);
assign n__112 = ~(tp2);
assign n__109 = ~(tp4);
assign n__10 = ~(io_pc_load);

endmodule